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A dual-top metal cmos process for under-pad devices
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A top metal and pad technology, applied in the field of double top metal CMOS process, can solve problems such as inability to realize DUP, and achieve the effects of controllable cost, improved flexibility and wide application range
Active Publication Date: 2021-12-28
XIAN MICROELECTRONICS TECH INST
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[0004] To sum up, in the 0.13-3μm CMOS process, products with fewer metal layers cannot achieve DUP
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Embodiment 1
[0075] Example 1, 3μm silicon gate CMOS double top layer metal process
[0076] Modify the design rules to allow DUP. When designing, place the active area of the circuit CMOS device and the polycrystalline pattern under the metal 1 pad to realize DUP, and follow the steps below to tape out.
[0077] Step 1, forming an active region,
[0078] Use an N-type doped wafer with a resistivity of 1 Ohm cm and a crystal orientation of (100) as the silicon substrate. The resistivity corresponds to a higher doping concentration. pad oxygen and Silicon nitride, then, define the field area by photolithography and etching silicon nitride, the area where the silicon nitride is etched will form the field area in the future, the area covered by silicon nitride is the active area, and the active area is divided into The active area of NMOS and the active area of PMOS;
[0079] Step 2, forming a P well,
[0080]Through photolithography and implantation, a P well is formed in the ac...
Embodiment 2
[0095] Example 2, 0.5 μm silicon gate CMOS double top layer metal process
[0096] Modify the design rules to allow DUP. When designing, place the CMOS device with a complete circuit, including the active area, polycrystalline, hole and metal 1 pattern, under the metal 2 pad to realize DUP, and tape it out according to the following steps.
[0097] Step 1, forming an active region,
[0098] Using a P-type doped wafer with a resistivity of 20 Ohm·cm and a crystal orientation of (100) as the silicon substrate, firstly grow the wafer with a thickness of pad oxygen and The silicon nitride, then, define the field area by photolithography and etching silicon nitride, the area where the silicon nitride is etched will form the field area in the future, the area covered by silicon nitride is the active area, and the active area is divided into The active area of NMOS and the active area of PMOS;
[0099] Step 2, forming N well and P well,
[0100] Through photolithography an...
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Abstract
The double top layer metal CMOS process of the device under the pad of the present invention forms an active region on a silicon substrate, then forms a P well on the NMOS active region, forms an N well on the PMOS active region, and then forms Field oxide layer and threshold implantation are performed to form gate oxide layer and polycrystalline gate, and then passivation etched silicon substrate is obtained according to 0.13-0.8 μm silicon gate CMOS process and greater than 0.8 μm and less than 3 μm silicon gate CMOS process, and the completion The existing standard thickness top metal CMOS process, finally by adding a metal deposition, photolithography and etching process, and then cooperate with the alloy operation to obtain a circuit with a thicker metal thickness at the pad, the metal thickness of the pad is increased; it can fully Buffering the stress existing in the bonding process is applicable to products with any number of metal layers, and has a wide range of applications. It not only improves the flexibility of the design, does not have any restrictions on the layout of the circuit layout, but also reduces the chip area.
Description
technical field [0001] The invention relates to the technical field of silicon microelectronics, in particular to the technical field of ultra-large-scale integrated circuit processing, in particular to a double-top-layer metal CMOS process for devices under pads. Background technique [0002] In the large-size CMOS process larger than 3μm, the number of pads is small, and the area occupied in the chip is small. However, as the CMOS process shrinks in proportion to Moore's law, the device size will shrink rapidly, and the bonding process will reduce the size of the device. Due to limitations, the size of pads decreases slowly; at the same time, the complexity of chip functions leads to an increase in the number of input and output pads, so the area occupied by pads in the chip is getting larger and larger. For the 0.13-3μm CMOS process, the thickness of the top layer metal is about 0.9-1.5μm, which cannot buffer the large stress in the bonding process. Therefore, the design ...
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