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FPGA-based SDIO interface test equipment and method

An interface test and equipment technology, applied in the field of SDIO interface test equipment, can solve the problems of high test cost, low flexibility, and inability to test, and achieve the effect of simplifying hardware design, increasing flexibility, and reducing test cost

Active Publication Date: 2020-02-11
FUZHOU ROCKCHIP SEMICON
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, this test method requires an external SDIO card with specific functions and a matching software driver. Any SDIO card does not contain all the contents of the SDIO protocol. If some tests need to be added and this SDIO card does not have this function, then it will not be possible. test
If the SDIO card manufacturer stops production or the SDIO test of another SOC does not use this SDIO card, then the software driver must be rewritten and the hardware must be redesigned, resulting in high test cost and low flexibility.

Method used

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  • FPGA-based SDIO interface test equipment and method
  • FPGA-based SDIO interface test equipment and method
  • FPGA-based SDIO interface test equipment and method

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Embodiment Construction

[0030] FPGA-based SDIO interface test equipment of the present invention is to use FPGA to design an SDIO card based on SDIO3.0 agreement, and this SDIO card can customize the parameter of card (such as the maximum bit width supported, whether there is a memory function), This makes this universal SDIO card meet the test requirements. If it is necessary to add tests, it is only necessary to modify the software driver, such as reconfiguring parameters, and the hardware platform does not need to be redesigned.

[0031] see figure 1 As shown, during the test, the SDIO card is connected to the SDIO interface of the SOC through corresponding pins; the pins include sdio_det, sdio_clk, sdio_cmd and sdio_data[3.0].

[0032] Another example figure 2 As shown, on the hardware structure, the SDIO card includes a CMD processing module, a CIA module, a command response module and a read-write test module, and the CMD processing module is connected to the order response module and the re...

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Abstract

The invention provides FPGA-based SDIO interface test equipment and method. The FPGA is used to design a virtual SDIO card based on the SDIO 3.0 protocol to replace the existing physical SDIO card, and the virtual SDIO card comprises a CMD processing module, a CIA Module, a command response module and a read-write test module, wherein the CMD processing module is respectively connected to the command response module and the read-write test module, and the command response module is also connected to the CIA module that can provide CCCR registers, FBR registers and CIS registers to customize the information meeting the requirements of FT testing, so that the test equipment is universal, thereby not only greatly increasing the flexibility of the test, but also simplifying the hardware designand reducing the test cost.

Description

technical field [0001] The invention relates to a testing device and method for an SDIO interface. Background technique [0002] SDIO (Secure Digital Input and Output) defines a peripheral interface on the SD standard. An important difference between it and the SD card specification is the addition of a low-speed standard. The SDIO card only needs SPI and 1-bit SD transfer mode. The target application of low-speed cards is to support low-speed IO capabilities with minimal hardware overhead. Low-speed cards support applications such as modems, barcode scanners, and GPS receivers. High-speed cards support network cards, TV cards, and combination cards. The combination card refers to memory + SDIO. For the combination card, the operation requires full speed and 4BIT transmission mode, which is stipulated by the SDIO1.0 standard. [0003] SDIO is one of the most important interface technologies for embedded systems in the future, so the current mobile SOC (System OnChip) pro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317
CPCG01R31/31713
Inventor 黄世凯陈燕丽林兆强
Owner FUZHOU ROCKCHIP SEMICON
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