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Method for forming semiconductor and semiconductor device

A technology for semiconductors, isolation regions, used in semiconductor devices, semiconductor/solid state device manufacturing, electro-solid devices, etc., to solve problems such as increasing the complexity of processing and manufacturing ICs

Active Publication Date: 2020-02-11
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This shrinking also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances

Method used

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  • Method for forming semiconductor and semiconductor device
  • Method for forming semiconductor and semiconductor device
  • Method for forming semiconductor and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0058] Example 1 is a method for forming a semiconductor comprising: forming isolation regions over a bulk semiconductor substrate; recessing the isolation regions, wherein top portions of semiconductor strips between the isolation regions protrude higher than the The top surface of the region is isolated to form a fin group, and the fin group includes: a plurality of inner fins; and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins; Fin spacers are formed on the sidewalls of the inner fins, the first outer fins, and the second outer fins, wherein the fin spacers include: outer fin spacers located on the outer sides of the first outer fins wall, wherein the outer sidewall faces away from the set of fins, and the outer fin spacer has a first height; and an inner fin spacer, located on an inner sidewall of the first outer fin, wherein the The interior sidewall faces the plurality of interior fins, and the interior fin spacers have a second...

example 10

[0067] Example 10 is a method for forming a semiconductor comprising: forming a gate stack on a plurality of semiconductor fins, wherein the plurality of semiconductor fins includes: a plurality of inner fins; and a first outer fin and a second outer fin , on opposite sides of the plurality of inner fins; and epitaxially growing an epitaxial region based on the plurality of semiconductor fins, wherein a first height of the epitaxial region measured along an outer sidewall of the first outer fin Less than a second height of the epitaxial region measured along an interior sidewall of the first exterior fin.

[0068] Example 11 is the method of example 10, wherein the difference between the first height and the second height is greater than about 2 nm.

[0069] Example 12 is the method of example 10, wherein the epitaxial regions formed based on the plurality of semiconductor fins are merged.

[0070] Example 13 is the method of example 10, wherein the epitaxial regions formed b...

example 16

[0073] Example 16 is a semiconductor device comprising: a plurality of semiconductor fins, wherein the plurality of semiconductor fins include: a plurality of inner fins; and first outer fins and second outer fins located opposite to the plurality of inner fins a gate stack on sidewalls and top surfaces of the plurality of semiconductor fins; a fin spacer on one side of the gate stack, wherein the fin spacer includes: a first outer fin a spacer and a second outer fin spacer, wherein the first outer fin spacer and the second outer fin spacer have a first height; and an inner fin spacer located between the first outer fin spacer and Between the second outer fin spacers, wherein the inner fin spacers have a second height less than the first height; and a semiconductor region extending into the space between each pair of the fin spacers.

[0074] Example 17 is the device of example 16, wherein the difference between the first height and the second height is greater than about 2 nm...

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PUM

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Abstract

The disclosure relates to a method for forming a semiconductor and a semiconductor device. A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductorfins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of thefirst outer fin.

Description

technical field [0001] The present disclosure generally relates to methods for forming semiconductors and semiconductor devices. Background technique [0002] Technological advances in integrated circuit (IC) materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (eg, the number of interconnected devices per chip area) typically increases while geometry size decreases. This downscaling process often provides benefits by increasing production efficiency and reducing associated costs. [0003] This scaling has also increased the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. For example, Fin Field Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structure of the FinFET and the method of manufacturing th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823412H01L21/823431H01L27/0886H01L21/823814H01L29/66545H01L29/6656H01L29/7848H01L29/165H01L29/665H01L29/785H01L29/41791H01L29/66795H01L21/31116H01L21/823468H01L21/02293H01L29/7855H01L21/762H01L29/0847H01L21/823437H01L21/823481
Inventor 黄玉莲
Owner TAIWAN SEMICON MFG CO LTD