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Double data rate synchronous dynamic random access memory ('ddr sdram') data strobe signal calibration

A technology of data strobe signal and data signal, which is applied in the direction of digital memory information, static memory, information storage, etc., and can solve problems such as data errors

Active Publication Date: 2020-02-14
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While this technique can improve upon the straightforward techniques described above, effects such as crosstalk can cause data errors during mission mode operation

Method used

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  • Double data rate synchronous dynamic random access memory ('ddr sdram') data strobe signal calibration
  • Double data rate synchronous dynamic random access memory ('ddr sdram') data strobe signal calibration
  • Double data rate synchronous dynamic random access memory ('ddr sdram') data strobe signal calibration

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Embodiment Construction

[0018] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0019] References herein to "SDRAM" or "DDR" memory components are to be understood as contemplating any SDRAM within the broader class of Synchronous Dynamic Random Access Memory ("SDRAM"), and do not limit the scope of the solutions disclosed herein. Restricted to a specific type or generation of SDRAM. Furthermore, certain embodiments of the solutions disclosed herein may be applicable to DDR, DDR-2, DDR-3, Low Power DDR ("LPDDR") or any subsequent generation of SDRAM.

[0020] The terms "central processing unit" ("CPU"), "digital signal processor" ("DSP") and "graphics processing unit" ("GPU") are non-limiting examples of processors that may reside in a PCD. Unless otherwise stated, these terms are used interchangeably herein.

[0021] The te...

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Abstract

In calibrating the phase skew between an SDRAM data strobe ('DQS') signal and data ('DQ') signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests mayemulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.

Description

Background technique [0001] A computing device such as a desktop computer, laptop or tablet computer, smartphone, portable digital assistant, portable game console, etc., includes one or more processors (such as a central processing unit, graphics processing unit, digital signal processor, etc.) and one or more memories. To facilitate higher throughput, such memory may be of a type capable of high speed operation, such as double data rate synchronous dynamic random access memory ("DDR SDRAM"). [0002] Synchronous DRAM or SDRAM utilizes a source synchronous memory interface in which the data source ("DQ") signal during data transfers is relied upon to provide the data strobe ("DQS") signal used by the destination of the data transfer to (channel) to capture such data signals as they are transmitted to the target. In DDR SDRAM, the DQ signal is sampled (ie, latched) at the target by both rising and falling edges of the DQS signal. [0003] Dense routing of circuit routing ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/02G11C7/10G11C29/12G11C29/42
CPCG11C7/1084G11C7/1093G11C29/022G11C29/023G11C29/028G11C29/1201G11C29/42G11C2207/2254G11C29/12015G11C29/50012G11C29/38G11C11/4076G11C11/409
Inventor L·N·加米尼S·慕克吉
Owner QUALCOMM INC
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