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Semiconductor parameter testing mechanism

A parametric testing and semiconductor technology, which is used in the testing of single semiconductor devices, conveyor objects, transportation and packaging, etc., can solve the problems of low work efficiency, large test errors, and high labor costs, so as to improve production efficiency and reduce measurement errors. Effect

Pending Publication Date: 2020-02-28
江阴亨德拉科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional test method is to manually use corresponding measurement tools to test the performance of packaged semiconductor products such as current and parameters. The test error is large, the work efficiency is low, and the labor cost is high. As a result, the economic benefits of the enterprise cannot be improved.

Method used

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  • Semiconductor parameter testing mechanism
  • Semiconductor parameter testing mechanism
  • Semiconductor parameter testing mechanism

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Embodiment Construction

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0040] see Figure 1-Figure 11 , a kind of electric current testing device that the present invention relates to, comprises machine board 1, and the top surface of described machine board 1 is provided with conveying channel 2 in parallel, and the top of described conveying channel 2 is provided with cover plate 8, and described conveying The flow channel 2 is provided with a feeding area, a testing area and a buffer area in sequence along the feeding di...

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Abstract

The invention relates to a semiconductor parameter testing mechanism, which comprises a delivery flow channel, wherein a first buffer assembly, a positioning assembly and a second buffer assembly aresequentially arranged in a material delivery direction of the conveying flow channel, a parameter testing assembly is arranged above the positioning assembly; the first buffer assembly is used for controlling products to be tested to be delivered orderly, the positioning assembly is used for positioning the products to be tested, the parameter testing assembly is used for testing parameters of theproducts to be tested, and the second buffer assembly is used for controlling the tested products to be delivered orderly. The semiconductor parameter testing mechanism provided by the invention hasthe advantages of being automatic, reducing measurement errors and improving production efficiency.

Description

technical field [0001] The invention relates to a semiconductor parameter testing mechanism, which belongs to the technical field of semiconductor testing. Background technique [0002] With the continuous development of modern technology, electronic products such as computers and mobile phones are becoming more and more popular, and have become an indispensable part of our lives. The core units of electronic products such as computers and mobile phones are closely related to semiconductors. The semiconductor production process consists of wafer fabrication, wafer testing, chip packaging, and post-package testing. After plastic sealing, a series of operations are carried out, such as post-curing, cutting and forming, electroplating and printing. Among them, the post-packaging testing process is to conduct various tests on its performance indicators to ensure that the quality passes before shipment. The traditional test method is to manually use corresponding measurement t...

Claims

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Application Information

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IPC IPC(8): G01R31/26B65G47/88
CPCB65G47/8807G01R31/26
Inventor 陈伟徐勇叶建国韩宙
Owner 江阴亨德拉科技有限公司