FPGA-based variable symbol sampling rate raised cosine filter

Abstract

The invention relates to an FPGA-based variable symbol sampling rate raised cosine filter, which comprises L + 1 high-speed sampling modules and L address calculation modules, wherein N = KL, K is thenumber of sampling points of each symbol, L represents that the cut-off time length of the filter is L symbols, and the number of filter coefficients is N + 1; L+ 1 high-speed sampling modules sequentially delay one clock period for sampling, the output ends of the high-speed sampling modules are connected to multipliers respectively, the output ends of the multipliers are connected to an adder,and the adder performs addition operation on L + 1 paths of signals input in parallel and is used for outputting raised cosine filtering signals; the device further comprises L ROM memories, the ROM memories are used for storing raised cosine filter coefficients h (n), n is equal to 0, 1, 2-N-1, and each ROM memory is connected with an address calculation module and used for calculating the address of the subsequent ROM memory. The scheme can adapt to a variable symbol sampling rate, and consumed FPGA multiplier resources do not change along with the symbol sampling rate.

Description

technical field [0001] The invention relates to the field of filters, in particular to an FPGA-based variable symbol sampling rate raised cosine filter. Background technique [0002] In modern communication systems, in order to reduce the influence of intersymbol interference, make the transmitted signal more suitable for channel transmission, and improve the transmission quality of the communication system, raised cosine (or square root raised cosine) filters are usually used as pulse shaping filters. The unit impulse response of the raised cosine filter at the sending end is: [0003] [0004] Among them, R is the roll-off silver, t is the time, and T is the symbol period. [0005] When the raised cosine filter is implemented, FPGA hardware can be used to implement it. Since the symbol rate is different from the output rate of the raised cosine filter, it is necessary to upsample first and digitize the publicity (1) before using the filter structure. Implement a struc...

AI Technical Summary

Problems solved by technology

[0006] The above-mentioned raised cosine filter structure is the same as the general filter block structure, which is mainly completed by multiplying and accumulating, but the filter structure is fixed and cannot adapt to changing symbol sampling rates

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