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FPGA-based multi-encoder protocol free conversion IP core and method

A technology of encoders and protocols, applied in the field of free conversion of IP cores of various encoder protocols, to achieve the effects of wide application range, high synchronization, and high integration

Active Publication Date: 2020-03-24
武汉华之洋科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this kind of infrared sensor, in addition to the need for real-time encoder position information, its protocol is often customized, not a standard common protocol

Method used

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  • FPGA-based multi-encoder protocol free conversion IP core and method
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  • FPGA-based multi-encoder protocol free conversion IP core and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] see figure 1 As shown, the embodiment of the present invention provides an FPGA-based IP core for free conversion of various encoder protocols, including: a basic IP core module, a peripheral IP core module, and a custom IP core module connected to each other through the Avalon bus.

[0055] Among them, the peripheral IP core module is used to obtain the control word written by the host computer. The basic IP core module is used to configure the control register of the self-defined IP core module according to the control word, so as to realize the selection of the input and output protocols, thereby enabling the corresponding state machine. Specifically, when the basic IP core module configures the control registers of the custom IP core module, the configuration information includes the input protocol selection (including baud rate settings, information digits, and command settings) enabling signals; the output protocol selection (including baud rate setting, bit sett...

Embodiment 2

[0077] Based on the same inventive concept, an embodiment of the present invention also provides a method for free conversion of multiple encoder protocols based on the above-mentioned IP core, and the method includes the following steps:

[0078] A. The peripheral IP core module obtains the control word written by the host computer; in actual operation, the content of the control word can include the number of input and output ports, protocol selection, baud rate selection, serial port enable, serial port command word settings, etc.

[0079] B. The basic IP core module configures the control register of the self-defined IP core module according to the acquired control word, realizes the selection of input and output protocols, and enables the corresponding state machine.

[0080] C. The custom IP core module performs encoder data acquisition, protocol conversion and output data to the corresponding destination machine; and the data acquisition and data output process are all g...

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Abstract

The invention discloses an FPGA-based multi-encoder protocol free conversion IP core and method, and relates to the technical field of industrial control. The FPGA-based multi-encoder protocol free conversion IP core comprises a peripheral IP core module used for obtaining a control word written by an upper computer, a basic IP core module which is used for configuring a control register of the self-defined IP core module according to the control word to realize selection of input and output protocols so as to enable a corresponding state machine, and a self-defined IP core module which is connected with an external encoder and at least one destination machine and is used for carrying out encoder data acquisition and protocol conversion and outputting data to the corresponding destinationmachine, wherein the data acquisition and data output processes are realized in a manner of generating a time sequence of a required interface protocol under the control of the corresponding state machine. According to the FPGA-based multi-encoder protocol free conversion IP core, parallel processing, synchronous acquisition and on-demand conversion and output of encoder data are realized, and thereal-time performance and synchronism of information are high, and the defect of inconsistent encoder protocols is overcome.

Description

technical field [0001] The invention relates to the technical field of industrial control, in particular to an IP (Intellectual Property, intellectual property) core and method for free conversion of various encoder protocols based on an FPGA (Field Programmable Gate Array). Background technique [0002] At present, encoder applications have already penetrated into various fields of industrial control, and there are many types of encoder interfaces on the market, including the commonly used incremental A, B, and Z-phase photoelectric encoders, RS422 asynchronous serial ports, SSI Protocol formula, Biss_c protocol formula, etc. In some applications requiring high precision, such as: high-precision turntables, photoelectric theodolites, infrared anti-scan control systems, etc., HEIDENHAIN encoders based on the ENDAT2.2 protocol are more reliable application choices. [0003] In the traditional servo drive control system, the scheme matching the encoder and the driver protocol...

Claims

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Application Information

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IPC IPC(8): G06F13/38H04L29/06G05B19/042
CPCG05B19/0423G06F13/382G06F2213/3852H04L69/08H04L69/26
Inventor 柯洋徐亚飞程维福谌昊赵志刚
Owner 武汉华之洋科技有限公司
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