A chip full-function self-test system and method based on FPGA platform

Abstract

This application discloses a chip full-function self-test system and method based on FPGA platform, including: a conveyor belt, an image sensor, an FPGA test bench and a two-way stepping motor of a cloud platform; wherein, the conveyor belt is used to sequentially transmit the tested chip To the bottom of the image sensor; the image sensor is used to transmit the silk screen image of the chip under test to the FPGA test bench; the FPGA test bench is used to read the silk screen information through LeNet, and the full-function test of the chip under test corresponding to the silk screen information can be called and executed program, find the configuration information about the test pin connection mode inside the FPGA corresponding to the test executable program, complete the pin connection matching and chip loading test, and also be used to control the dual-way stepping motor pair of the gimbal according to the full-function test results After testing, the chips under test are classified. In this way, full-automatic chip testing can be realized, which can greatly improve the accuracy and efficiency of chip full-function testing, and reduce manpower, material resources and time costs.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a chip full-function self-testing system based on an FPGA platform and a method thereof. Background technique [0002] Under the general trend of localization of chips, the "core-making" industry is booming. While reducing chip prices, breaking technical barriers, and promoting the production of high-tech products, consumers are also faced with the uneven quality of chips. The problem of difficult to control the chip yield rate. In order to help buyers better identify the quality of chips purchased in batches, full-function testing of chips before use has become a necessary link. [0003] The traditional full-function test of chips requires a lot of manpower, material resources and time costs. The test process is long and the possibility of errors is high. Developers are constantly optimizing the test process and trying to reduce the manpower and time investment of the test. However,...

AI Technical Summary

Problems solved by technology

[0003] Traditional full-function testing of chips requires a lot of manpower, material resources and time costs. The test process is long and the possibility of errors is high. Developers are constantly optimizing the test process and trying to reduce the manpower and time input for testing. However, after optimization However, the scheme still requires testers to join, manually connect chip pins, test result statistics and test chip screening, the whole process is inefficient and the probability of error is still high

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