Time domain interleaved ADC multi-phase clock generation circuit

A multi-phase clock and generation circuit technology, applied in electrical components, analog-to-digital converters, code conversion, etc., can solve the problems of poor flexibility of clock duty cycle high-level overlap control, timing continuity problems, complexity, etc. Achieve the effects of good timing relationship, adjustable high-level overlap, and adjustable duty cycle

CN110971233APending Publication Date: 2020-04-07XIDIAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2020-04-07

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Abstract

The invention discloses a time domain interleaved ADC multi-phase clock generation circuit comprising a signal conversion module used for generating first, second, third and fourth output signals according to first and second input signals; a first frequency division module and a second frequency division module used for carrying out frequency division processing on the first output signal, the second output signal, the third output signal and the fourth output signal to obtain a first frequency division signal and a second frequency division signal; a signal coupling module used for carryingout mutual coupling processing on the first frequency division signal and the second frequency division signal to obtain a frequency division coupling signal; a multi-channel clock signal module usedfor carrying out signal processing on the frequency division coupling signal according to a preset signal processing rule to obtain a multi-channel clock signal; and a driving circuit module used forcorrecting the multi-channel clock signal to obtain a final multi-phase clock signal. According to the invention, the output ends of the first frequency division module and the second frequency division module are subjected to mutual coupling processing, so that the continuity of frequency division signals is enhanced, and the sequential relationship between the signals is better.
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Description

technical field

[0001] The invention belongs to the technical field of ADC analog-to-digital converters, and in particular relates to a time-domain interleaved ADC multiphase clock generation circuit. Background technique

[0002] The high speed and high precision of an analog-to-digital converter (Analog-to-Digital Converter, referred to as ADC) has always been the relentless pursuit of people. As a bridge between analog circuits and digital circuits, analog-to-digital converters have been facing many challenges in performance improvement. In the field of high-speed signal processing, factors such as technology have greatly limited the conversion rate of the analog-to-digital converter.

[0003] In recent years, with the development of the field of analog-to-digital converters, the demand for clock sampling frequency of analog-to-digital converters has become higher and higher. It is difficult to improve the clock frequency of single-channel analog-to-digital converters ac...

Examples

Embodiment 1

[0062] See figure 1 , figure 1 It is a schematic structural diagram of a time-domain interleaved ADC multi-phase clock generation circuit provided by an embodiment of the present invention. This embodiment provides a time-domain interleaved ADC multi-phase clock generation circuit, the time-domain interleaved ADC multi-phase clock generation circuit includes a signal conversion module, a first frequency division module, a second frequency division module, a signal coupling module, a multi-channel Clock signal module, drive circuit module, wherein,

[0063] A signal conversion module, configured to generate a first output signal, a second output signal, a third output signal and a fourth output signal according to the first input signal and the second input signal;

[0064] The first frequency division module is connected to the signal conversion module, and is used for performing frequency division processing on the first output signal and the second output signal to obtain ...