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Signal processing system and method for MIPI C-PHY

A technology of signal processing and processing method, applied in the field of signal processing, can solve problems such as affecting the display effect, and achieve the effect of maintaining signal quality, reducing signal jitter and better display effect

Pending Publication Date: 2020-04-07
ANHUI SEMICON INTEGRATED DISPLAY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

thus affecting the display effect

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  • Signal processing system and method for MIPI C-PHY
  • Signal processing system and method for MIPI C-PHY
  • Signal processing system and method for MIPI C-PHY

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Embodiment Construction

[0019] The specific implementation manner of the present invention will be described in further detail below by describing the best embodiment with reference to the accompanying drawings.

[0020] The present invention is a method for reducing jitter during logic state transition, the main purpose of which is to reduce signal jitter during logic state transition, maintain signal quality, and optimize display effect. Including clock unit; FPGA unit; C-PHY signal receiver. The clock unit is used to provide the working clock of FPGA and provide the minimum clock unit. The FPGA unit receives the A / B / C 3-wire signal, and delays the signal accordingly by counting to achieve the purpose of synchronous output. The C-PHY signal receiver receives 3-wire data for decoding and then sends it to the display screen for display, including:

[0021] A signal processing system of MIPI C-PHY, including FPGA unit, clock unit, signal receiver, the input end of FPGA unit inputs the 3-wire signal ...

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Abstract

The invention discloses a signal processing system and method for an MIPI C-PHY, and the system comprises an FPGA unit, a clock unit, and a signal receiver, and a 3-wire signal of the MIPI C-PHY is input to the input end of the FPGA unit; the clock unit is connected with the FPGA unit and used for providing a working clock for the FPGA unit; the FPGA unit delays the received 3-wire signal and sends the delayed 3-wire signal to the input end of the signal receiver; and the signal receiver receives the signal, decodes the signal and outputs the decoded signal. The method has the advantages thatthe signals are delayed respectively, so that the signals A, B and C of the 3-wire signals are delayed and then logic state conversion is carried out at the same time to realize synchronous output, signal jitter is reduced, signal quality is maintained, and a display effect is better.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to a MIPI C-PHY signal processing system and method. Background technique [0002] The MIPI alliance is the Mobile Industry Processor Interface (MIPI for short) alliance. The communication interface standard determined therefrom is used for communication between the host computer and peripheral devices. MIPI C-PHY is a new high-speed communication interface that satisfies the drive of high-resolution display modules in recent years. It uses three signal lines for communication. The three signal lines transmit high, medium and low ternary signals respectively. The clock signal is Buried in a ternary signal. C-PHY's three-valued signal has inherent jitter when the logic state changes, which degrades the signal quality. Thus affecting the display effect. Therefore, there is a technical demand for reducing the jitter generated when the logic state changes at the receiving end of the...

Claims

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Application Information

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IPC IPC(8): H04L12/841H04L12/26
CPCH04L47/283H04L43/0852H04L43/087
Inventor 沈利军赵铮涛曹绪文晋芳铭
Owner ANHUI SEMICON INTEGRATED DISPLAY TECH CO LTD