2 results about "Ternary signal" patented technology

The invention provides a three-valued logic four-state gate circuit. The three-valued logic four-state gate circuit comprises an output module and a control module, the output module comprises a first resistor, a second resistor, a first switch assembly and a second switch assembly, the first resistor and the second resistor are connected in series, the first switch assembly is arranged between the first resistor and power voltage, and the second switch assembly is arranged between the second resistor and the ground. The control module generates control signals of the first switch assembly and the second switch assembly according to a three-valued input signal and a three-valued enable signal which are connected, so that when the logic value of the three-valued enable signal is 2, the logic value which is the same as the logic value of the three-valued input signal is obtained at the output end of the circuit, and when the logic value of the three-valued enable signal is 0 or 1, the logic value of the three-valued enable signal is not equal to the logic value of the three-valued input signal. And the first switch assembly and the second switch assembly are switched off, so that a high-resistance state is formed at the output end of the circuit, namely, three-value input and four-state output are realized, and the system integration level and the information transmission efficiency are improved.

This application discloses a method, apparatus, equipment, and storage medium for verifying tobacco packaging inspection data, relating to the field of tobacco technology. The method addresses the problems of low efficiency, poor sample consistency, ambiguous fault location, and difficulty in data traceability associated with manual verification of tobacco packaging inspection. It uses digital images to replace physical defective samples and combines signal synchronization and logical comparison technologies to achieve automated verification. This requires no modification to the original hardware architecture, allows for simultaneous verification by multiple devices, reduces the cost of physical samples, and avoids safety risks. Step S1 establishes a unified defective sample benchmark to eliminate human bias; Step S2 achieves verification without physical inspection, without interfering with production; Step S3 calibrates signal timing to ensure the effectiveness of comparison; Step S4 extracts core statistical features to provide a basis for quantitative judgment; Step S5 accurately distinguishes fault types through ternary signal logical matching; Step S6 outputs structured results to support data traceability and equipment status analysis.