Time-delay locking loop

Abstract

The invention is concerned with the delay time locking loop circuit, it is higher logical control accuracy and faster response characteristic, and restrains the effect leading by the power fluctuation and the molestation from the transmission line. It is: inserts the independent double-loop (the signal phase locking loop and the signal cycle locking loop) sample loop structure in the signal path, uses the ternary signal sample method to process phase (the earlier or later logical judgment) sample / text and signal cycle (the narrow or width logic judgment) sample / text for the clock / data signal, changes the phase and space between the ternary sample points by the voltage controlling delay line if the judgment exists deviation, processes sample of the signal phase and cycle again until lock the signal phase and cycle finally.

Description

technical field [0001] The invention relates to a signal sampling circuit, in particular to a delay locked loop circuit. Background technique [0002] In many microelectronic applications, especially high-speed communication systems, signal quality increasingly depends on the performance of the clock system. Phase-locked loop PLL and delay-locked loop DLL can meet the low phase drift characteristics or low phase error requirements of the system, and are widely used in FM demodulation in communication systems, frequency synthesis of digital communication, and carrier recovery under low signal-to-noise ratio etc. [0003] The basic components of the phase-locked loop PLL: phase detector PD, loop filter LPF and voltage-controlled oscillator VCO; as shown in Figure 1. By comparing the phase difference between the input signal and the output signal of the voltage-controlled oscillator, an error control voltage is generated to adjust the frequency of the voltage-controlled oscil...

AI Technical Summary

Problems solved by technology

However, since the DLL uses a voltage-controlled delay line, the delay for DLL locking must be a clock cycle. In order to avoid locking a non-1-cycle clock, the DLL needs to use complex control logic circuits to determine whether the lock is correct, which will Affects the response characteristics and metrics of the system

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