Method for processing clock stretching through I3C bus, equipment and storage medium
A clock and bus technology, applied in the field of I3C bus processing clock stretching, can solve problems such as the impact of server components, and achieve the effect of avoiding protocol incompatibility
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[0042] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0043] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are to distinguish two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present invention, which will not be described one by one in the subsequent embodiments.
[0044] It should be noted that the standard process of I2C reading registers is: 0. Master initiates START; 1. Master sends I2Caddr (7bit) and w operation 1 (1bit), waiting for ACK; 2. Slave sends ACK; 3. Master sends regaddr ( 8bit), waiting for AC...
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