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A method, device and storage medium for i3c bus processing clock stretching

A clock and bus technology, applied in the field of I3C bus processing clock stretching, can solve problems such as server component impact, and achieve the effect of avoiding protocol incompatibility

Active Publication Date: 2021-07-30
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The I3C protocol does not support this operation, which has a great impact on existing server components

Method used

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  • A method, device and storage medium for i3c bus processing clock stretching
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  • A method, device and storage medium for i3c bus processing clock stretching

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Embodiment Construction

[0042] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0043] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are to distinguish two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present invention, which will not be described one by one in the subsequent embodiments.

[0044] It should be noted that the standard process of I2C reading registers is: 0. Master initiates START; 1. Master sends I2Caddr (7bit) and w operation 1 (1bit), waiting for ACK; 2. Slave sends ACK; 3. Master sends regaddr ( 8bit), waiting for AC...

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PUM

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Abstract

The invention discloses a method for I3C bus processing clock stretching, comprising steps: a master device determines the state of a slave device; in response to the slave device being in an idle state, establishing communication with the slave device; in response to the slave device The device generates a clock stretching operation, the slave device replies address data to the master device and interrupts the communication with the master device; in response to the end of the clock stretching operation, the master device obtains the address data according to the address data data generated by the slave device after the clock stretching operation. The invention also discloses a computer device and a readable storage medium. The scheme disclosed by the present invention can obtain the bottom-level and the most authentic original data, and strictly follow the I3C protocol. Through the control of the bus, it replaces the I2C slave device with clock stretching to send a reply to the master device, avoiding clock stretching resulting in protocol incompatibility.

Description

technical field [0001] The invention relates to the communication field, in particular to a method, device and storage medium for I3C bus processing clock stretching. Background technique [0002] The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronics communication control. It is a special form of synchronous communication, which has the advantages of less interface lines, simple control mode, small device package, and high communication rate. [0003] I2C communicates information between devices connected to the bus through the serial data (SDA) and serial clock (SCL) lines. Each device has a unique address identification, and can be used as a transmitter or receiver (determined by the function of the device). The master is the device that initiates the data transfer on the bus and generates the clock signals that allow th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38G06F13/42
CPCG06F13/385G06F13/4282
Inventor 林宁亚
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD