Manufacturing method of split gate structure

Abstract

The invention relates to a manufacturing method of a split gate structure. The manufacturing method comprises the following steps that: a groove is formed in the surface of a wafer; the groove is filled with polycrystalline silicon; a mask layer is formed on a polycrystalline silicon surface in the groove according to a designed thickness; the mask layer is quantitatively etched, an etched thickness at least achieves the design thickness, so that the polycrystalline silicon surface with a plane surface is exposed, and the mask layer of the concave part of the polycrystalline silicon surface remains and serves as a morphology adjusting mask due to the fact that the thickness of the mask layer is larger than the design thickness; the polycrystalline silicon in the groove is etched downwardsuntil the morphology adjusting mask is separated from the polycrystalline silicon; and the separated morphology adjusting mask is removed, and the polycrystalline silicon in the groove is used as thebottom-layer polycrystalline silicon of the split gate. The morphology adjusting mask serves as an etching blocking structure in a polycrystalline silicon etching process, so that the etching speed ofpolycrystalline silicon in a concave position is smaller than the etching speed of polycrystalline silicon in other positions, and finally the bottom-layer polycrystalline silicon with a flat surfaceis obtained.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a split gate structure. Background technique [0002] In the split gate (Split Gate) manufacturing process, it is necessary to form a relatively flat underlying polysilicon 20 at the bottom of the trench (Trench) (see figure 1 ), the underlying polysilicon 20 is usually made of polysilicon 20 that fills up the trenches (see figure 2 ) formed by engraving back. [0003] However, figure 2 A gap 21 is usually formed in the middle of the polysilicon 20, and the gap 21 is specifically a joint of the polysilicon, but is filled with a large number of voids. Therefore, the polysilicon 20 will be affected by the loading effect / adjacency effect during the etching process, resulting in an uneven surface of the bottom polysilicon 20 finally formed (see Figure 3a , Figure 3b ). Moreover, for a wafer formed with multiple split gate structures, the...

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[0003] However, figure 2 A gap 21 is usually formed in the middle of the polysilicon 20, and the gap 21 is specifically the closing place of the polysilicon, but it is filled with a large number of voids

Therefore, the polysilicon 20 will be affected by the loading effect / adjacency effect during the etching process, resulting in an uneven surface of the bottom polysilicon 20 finally formed (see Figure 3a , Figure 3b )

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