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Chip test circuit, memory and wafer

A chip testing and circuit technology, which is applied in the field of chip testing circuits, memory and wafers, can solve the problems of poor reliability of chip test results and achieve the effect of improving reliability and yield

Pending Publication Date: 2020-05-08
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present disclosure is to provide a chip test circuit, memory and wafer, and then at least to a certain extent overcome the technical problem of poor reliability of chip test results caused by the limitations of related technologies

Method used

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  • Chip test circuit, memory and wafer
  • Chip test circuit, memory and wafer
  • Chip test circuit, memory and wafer

Examples

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Embodiment Construction

[0059] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present invention will be comprehensive and complete, and fully convey the concept of the example embodiments To those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted.

[0060] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship between one component of an icon and another component, these terms are used in this specification only for convenience, for example, according to the drawings. The direction of the example described. It can be understood that if the device of the icon is turned over...

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PUM

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Abstract

The invention relates to a chip test circuit, a memory and a wafer. The chip test circuit provided by the embodiment of the invention comprises: a test signal interface, which is used for receiving atest signal; a first electrostatic protection circuit, one end of which is connected to the test signal interface; a signal selection circuit, a first input end of which is connected to the other endof the first electrostatic protection circuit, a second input end of which is used for receiving a working signal, a control end of which is used for receiving a characteristic signal related to the test signal, and an output end of which is used for outputting the test signal or the working signal to a chip to be tested. According to the chip test circuit provided by the embodiment of the invention, a test result closer to the normal working state of the chip can be obtained, the reliability of the chip test result is improved, and then the yield in chip production and processing can be further improved.

Description

Technical field [0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a chip test circuit, a memory and a wafer. Background technique [0002] Generally, multiple testing procedures are involved in the production and processing of chips. For example, before the wafer is diced, it is necessary to conduct a preliminary test on the working electrical characteristics of each chip on the wafer to check whether the chip can work normally and whether it meets the specified standards. This test is usually performed on an automatic test equipment (Automatic Test Equipment, referred to as ATE), and the ATE clock is often multiplied by a frequency multiplier circuit and then a high-frequency clock is provided inside the chip for testing. In the existing test scheme, the test signal in the test mode directly enters the chip to be tested, which is different from the transmission path of the working signal in the working mode, and therefore, ...

Claims

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Application Information

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IPC IPC(8): G01R31/28H01L21/66
CPCG01R31/2801H01L22/34
Inventor 牟文杰
Owner CHANGXIN MEMORY TECH INC