Interposer circuit, substrate-on-wafer circuit and method for utilizing interface circuit
A circuit and intermediary technology, which is applied to a substrate-on-wafer-on-chip interposer and its utilization field, can solve the problems of heating of the interposer and the like
Active Publication Date: 2020-05-08
TAIWAN SEMICON MFG CO LTD
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
Capacitors can fail and can drain large amounts of DC power, making the interposer hot
Method used
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[0055] It should be understood that the following disclosure provides many different embodiments, or illustrations, for implementing different features of the invention. Specific illustrations of components and arrangements are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or desired characteristics of the device. Moreover, the description that the first feature is formed on or over the second feature includes the embodiment that the first feature and the second feature are in direct contact, and also includes other features formed between the first feature and the second feature, such that Embodiments in which the first feature and the second feature are not in direct contact. In addition, the present disclosure repeats reference numerals and / or letters in various ...
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The invention relates to an interposer circuit, a substrate-on-wafer-on-wafer circuit and a method for utilizing an interface circuit. The interposer circuit includes a substrate and a dielectric layer disposed on top of the substrate. The interposer circuit also includes two or more connection layers including a first connection layer and a second connection layer disposed in different depths ofthe dielectric layer. The interposer circuit includes a fuse disposed within the first connection layer. The first connection layer is coupled to a first power supply node, and the second connection layer is coupled to a first ground node. The interposer circuit also includes a first capacitor connected in series with the fuse and connected between the first connection layer and the second connection layer. The interposer circuit also includes a first microbump, a second microbump, and a third microbump on top of the dielectric layer such that the fuse is coupled between the first microbump and the second microbump and the first capacitor is coupled between the second microbump and the third microbump.
Description
technical field [0001] The present disclosure relates to an on-substrate on-wafer interposer and its utilization method, and more particularly to an on-substrate on-wafer-on-die interposer with a selective / programmable capacitor array and its utilization method. Background technique [0002] Chip on wafer on substrate (CoWoS) is a wafer-level multi-chip packaging method, which integrates many small chips (chiplets) and arranges them on an interposer. The chiplet may be a system on chip (SOC) bonded to the interposer via microbump connections (on top of the interposer). The interposer utilizes through-silicon vias (TSVs) to connect the TSVs from the bottom of the interposer to microbump connections on the substrate. The CoWoS interposer receives electrical power connections through solder-bump connections on the substrate and provides electrical power connections to the chiplets through micro-bump connections on top of the interposer. [0003] Simultaneous switching of smal...
Claims
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IPC IPC(8): H01L23/522H01L23/525
CPCH01L23/5222H01L23/5226H01L23/5256H01L23/5223H01L23/481H01L2224/16237H01L2224/16235H01L2224/81192H01L24/16H01L23/5382H01L23/49822H01L23/49827H01L2924/00014H01L2224/13099H01L23/62H01L23/642H01L2225/06517H01L2224/12105H01L24/17
Inventor 林亮臣张仕承
Owner TAIWAN SEMICON MFG CO LTD