Non-blocking cache missing processing method and device
A high-speed cache and processing device technology, applied in the direction of machine execution devices, electrical digital data processing, program control design, etc., to achieve the effect of improving comprehensive performance
Inactive Publication Date: 2020-05-12
核芯互联科技(青岛)有限公司
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Problems solved by technology
[0007] The purpose of the embodiments of the present invention is to provide a non-blocking cache miss processing method and device to solve the problems caused by the existing non-blocking Cache mechanism
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[0025] The implementation of the present invention will be illustrated by specific specific examples below, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0026] In the following description, for purposes of illustration rather than limitation, specific details, such as specific system architectures, interfaces, and techniques, are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
[0027] In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "conne...
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The invention discloses a non-blocking cache missing processing method and a device, and relates to the field of computer cache processing. The non-blocking cache missing processing device comprises abuffer table, a thread table, a cache, a plurality of hardware caches and a control processing module, and parameterized configuration is supported by table entries and addresses and data bit widthsof the caches so as to meet various application scenes of performance differentiation requirements. Through a non-blocking instruction cache structure and an instruction pre-fetching mode, an assemblyline is not suspended, and continuous processing of multiple missing requests is supported; pre-returning the storage data of the adjacent address for the external bus request caused by each missingthrough an optimized instruction pre-fetching strategy; the prefetching address is directly generated by a missing address high order, so that the conflict of bus request data cannot be caused; in addition, through a non-blocking data cache structure and an assembly line conflict resolution mode of the non-blocking data cache structure, the comprehensive performance of the data cache can be effectively improved.
Description
technical field [0001] Embodiments of the present invention relate to the field of computer caches, and in particular to a non-blocking cache miss processing method and device. Background technique [0002] For superscalar out-of-order execution processors, in order to maintain cache data consistency, a blocked Cache (high-speed cache) mechanism is often used. That is, when there is a missing request in the Cache, the pipeline is stopped until the data is returned from the next-level storage body, and the request is considered to be processed; the pipeline can continue to process the next request, and the time when the next-level storage body returns data determines to block the Cache s efficiency. However, pausing the pipeline when the cache is missing is a waste of resources. If the processor can continue to send the next request while waiting for the next level of storage to return data, the processing efficiency can be greatly improved. Rather than blocking the Cache m...
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Login to View More IPC IPC(8): G06F9/38
CPCG06F9/3814G06F9/3867
Inventor 陈伟杰
Owner 核芯互联科技(青岛)有限公司