Transistor structure and process method thereof

Abstract

A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain / source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundarydirectly connected to the second terminal of the channel region. The drain / source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain / source region is confined to an isolator, and sidewalls of the drain / source region are confined to spacers except sidewalls of the lower portion of the drain / source region. Compared with the prior art, low leakage current can exist in an off state of the transistor structure.

Description

technical field [0001] The invention relates to a transistor and its process method, in particular to a transistor with self-aligned three terminals and its process method. Background technique [0002] One of the most commonly used transistors is a metal oxide semiconductor field effect transistor formed on a planar silicon wafer, wherein the gate of the transistor is formed on the surface of the silicon wafer and is made of a thinner A dielectric such as silicon dioxide or a high-k material separates it. The other two ends of the transistor, namely the drain and the source, are formed below the surface of the silicon wafer. And when the size of the transistor needs to be reduced, a fin structure transistor (such as a fin field effect transistor (FinFET), a tri-gate transistor (tri-gate FET) or a double-gate (double-gate) transistor can be used. etc.), so that the size of the transistor can be further reduced from 22 nm to 7 nm, or smaller than the prior art. However, mo...

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Problems solved by technology

For example, in 10nm process technology, the channel length of the transistor needs to be greater than 100nm to reduce the off current of the transistor to 1 femtoampere per memory cell, which is very impractical

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