Method and system for training DQ and DQS signal duty ratios of DDR memory controller

Abstract

The invention provides a method and system for training DQ and DQS signal duty ratios of a DDR memory controller. The method comprises the following steps of: providing an initial duty ratio; findingout the size of the DQ eye pattern by delaying a DQS signal; and, recording the size of the DQ eye pattern by soft logic, then changing the value of the duty ratio control signal, finding out the sizeof a new DQ eye pattern, and checking whether the DQ eye pattern is enlarged or not, so that the DQ eye pattern is repeatedly adjusted to the maximum, and the corresponding DQ and DQS duty ratio settings when the DQ eye pattern window is maximum are obtained. According to the invention, the problem of duty ratio distortion of DQ and DQS signals can be solved, and the read-write speed and reliability of the memory controller are improved.

Description

technical field [0001] The invention relates to the technical field of DDR memory controllers, in particular to a training method and system for the duty cycle of DQ and DQS signals of a DDR memory controller. Background technique [0002] DDR SDRAM (Double Rate Synchronous Dynamic Random Access Memory) is generally called DDR, and it is a memory whose data transfer rate is twice that of SDRAM memory. In DDR, input and output data are synchronized with the rising and falling edges of the clock. [0003] The existing DDR cannot directly exchange data with the CPU, and needs to transmit data through the memory controller, so the read and write speed of the memory controller directly determines the performance of the computer system. The interface circuit between memory controller and DDR such as figure 1 As shown, where PHY represents the physical layer interface, and IOB represents the input and output buffer circuit. [0004] With the continuous improvement of DDR SDRAM p...

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Problems solved by technology

[0005] In view of this, the present invention provides a DQ and DQS signal duty cycle training method and system of a DDR memory controller, which can solve the problem of DQ and DQS signal duty cycle distortion

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