Chip failure analysis method for dynamically grabbing points

A chip and dynamic technology, which is applied in the direction of electronic circuit testing, measuring devices, instruments, etc., to achieve the effect of convenient and dynamic grasping points, avoiding moving test machines, and reducing development costs

Inactive Publication Date: 2020-06-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] This application provides a chip failure analysis method for dynamic point grabbing, which can solve the problem of developing FPGA programs or moving the testing machine for dynamic point grabbing in related technologies

Method used

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  • Chip failure analysis method for dynamically grabbing points
  • Chip failure analysis method for dynamically grabbing points
  • Chip failure analysis method for dynamically grabbing points

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Embodiment Construction

[0029] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0030] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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Abstract

The invention discloses a chip failure analysis method for dynamically grabbing points, and relates to the field of chip failure analysis. The method comprises the following steps of installing a chipto be tested on a PCB, wherein the PCB is at least provided with a chip connecting seat, a battery and a chip pin contact pin; connecting the chip to be tested with a testing machine through a pin onthe PCB; connecting the testing machine, the chip to be tested and the battery; sending an excitation mode to the to-be-tested chip through the test machine, wherein the excitation mode is used for enabling the to-be-tested chip to enter one of predetermined excitation states; disconnecting the test machine from the chip to be tested and the PCB, so that the problem that the testing machine needsto be moved for dynamically grabbing points at present is solved, and the effects of avoiding moving the test machine, not limiting the position of the test machine, maintaining the state of the chipand facilitating the dynamic point grabbing are achieved.

Description

technical field [0001] The present application relates to the field of chip failure analysis, in particular to a method for dynamic point-grabbing chip failure analysis. Background technique [0002] Integrated circuit chips will inevitably fail in the process of development, production and use. In order to find the cause of chip failure, it is necessary to conduct failure analysis on the failed chip. When locating the defect position of the failed chip, the method of dynamic point grabbing can be used. Commonly used technologies for dynamic point capture include Optical Beam Induced Resistance Change (OBIRCH) and Emission Microscope (EMMI). If the chip is in a specific state, the chip circuit will have a specific level state, and defective chips The following features may appear in some positions: 1. The thermal characteristics are different after laser irradiation, which in turn affects the current on the power supply; 2. Photons different from normal chips are emitted, s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851
Inventor 张雨田曾志敏张庆文
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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