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Static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing

A technology of simulated annealing and layout method, applied in the field of interconnect structure of reconfigurable arrays, can solve the problems of reduced routing rate, inability to accurately respond to position constraints, and inability to routing, and achieve the effect of improving routing rate

Pending Publication Date: 2020-06-16
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

There are location constraints of different types of computing resources in heterogeneous arrays. Traditional mapping schemes do not model such heterogeneous problems. Therefore, location constraints cannot be accurately reflected under heterogeneous arrays, so the throughput rate will drop. Can't even get through the problem

Method used

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  • Static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing
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  • Static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing

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Embodiment 1

[0032] Such as Figure 5 Lays out a dataflow graph into an array as shown. The array is a common heterogeneous array, and the array resources are divided into three categories, loop control, storage processing and general computing. The general-purpose computing unit, that is, PE (Processing Element), is the most numerous unit in the array; while the storage processing unit, that is, LS (Load and Store), is often distributed at the outermost periphery of the array, and its function is the most important, but it is more important than other types. The location constraints of resources are stricter; while the loop control unit LC (Loop Control) is a type of resource that is more important than PE, but the priority is not as good as LS.

[0033] In the multi-stage simulated annealing method, according to the importance of the resources of the heterogeneous reconfigurable array in the array, the layout process is divided into multiple stages according to different resource types....

Embodiment 2

[0041] The present invention mainly proposes a static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing. Taking six applications in MachSuite that are suitable for acceleration of static heterogeneous reconfigurable arrays as an example, from the two aspects of deployment rate and algorithm time Analyze the algorithm and interconnection quality from two angles, reflecting the technical effect of this patent:

[0042] Routing rate: The scale of the array structure used in this embodiment is 10×10. For each combination of algorithm and interconnection structure, the algorithm is repeatedly executed 50 times, and the number of successful completion of layout and wiring is recorded, and the proportion is taken as the ratio of routing. Rate. Table 1 shows different algorithms under different interconnection resource structures, such as Figure 4 , using the comparison of the pass rate of the two algorithms.

[0043] Table 1 Comparison of th...

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Abstract

The invention discloses a static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing, and relates to the field of interconnection architectures of reconfigurablearrays. The method is characterized in that the graph distance is utilized to construct the position constraint of the heterogeneous resources, and a staged simulated annealing method is utilized to separate the mutual influence of the heterogeneous resources in the same simulated annealing. According to the method, a novel cost function based on the graph distance is constructed to solve the problem that a traditional cost function is inaccurate in heterogeneous array modeling, and then a staged simulated annealing layout scheme is provided according to the characteristics of different heterogeneous units. Compared with a result obtained by applying a traditional scheme to a heterogeneous array, the multi-stage simulated annealing method applying the novel cost function can averagely improve the throughput rate by 29.6% under the condition of the same interconnection resources.

Description

technical field [0001] The invention relates to the field of interconnection architecture of reconfigurable arrays, in particular to a static heterogeneous reconfigurable array layout method based on multi-stage simulated annealing. Background technique [0002] The reconfigurable array processor is a new type of processor that is considered to have excellent custom configuration capabilities, can undertake data-intensive operations, and can obtain better operating frequencies than FPGAs to achieve high-performance operations. A compromise between flexibility and specificity, it can not only maintain a high performance relative to an application-specific integrated circuit (ASIC), but also achieve a high degree of freedom similar to an FPGA. Before each operation of the reconfigurable array, the configuration information is first received, and the configuration control module sends the configuration information to each execution unit and each interconnection resource. After ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392
CPCY02T90/00
Inventor 景乃锋行华彧蒋剑飞王琴绳伟光贺光辉
Owner SHANGHAI JIAO TONG UNIV
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