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Bus real-time synchronous control device

A technology of real-time synchronization and control device, applied in the direction of synchronization device, program control, computer control, etc., can solve problems such as less than ideal effect

Pending Publication Date: 2020-07-07
深圳市小步数控有限公司
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AI Technical Summary

Problems solved by technology

This method can improve real-time performance to a certain extent, but due to the influence of the operating system, the effect is not ideal

Method used

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  • Bus real-time synchronous control device

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Embodiment 2

[0031] Embodiment 2, on the basis of Embodiment 1, sample ZYNQ series XC7Z020 high-performance SOC of Xilinx, this device integrates dual A9 processors and a large-capacity FPGA. The dual A9 core adopts the Linux system operating system, and the measured real-time performance is between -100us-100us. One of the A9 cores is used for user interaction, Internet of Things and other functions, and the other A9 core is used for the calculation of motion control algorithms and EtherCAT protocol stack processing. FPGA completes timing transmission and reception of EtherCAT protocol, generation of synchronous clock, 100M Ethernet pipe, data cache, etc. A9 and FPGA communicate through the AXI bus. The bus clock is 100M, the bus data bit width is 32, and the communication speed is very fast. The A9 write cache time can be very short, which hardly affects the real-time calculation of the motion algorithm. The FPGA has a 4Mb FIFO space, and the CPU only needs to send the data to the FIFO ...

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Abstract

The invention discloses a bus real-time synchronous control device, and the device comprises a CPU and an FPGA / CPLD. The CPU completes man-machine and bus control and control algorithms after transplanting an operating system, and the FPGA / CPLD uniformly controls a bus communication mechanism and network control. The FPGA / CPLD parallel processing and time precise control characteristics are utilized, the FPGA / CPLD is used for completing the real-time communication function, and communication data sending jitter can be effectively controlled within the ns-level precision range. And meanwhile,the period is fixed, so the synchronization function can calculate the delay time of each slave station in advance through the data volume and the communication rate. Therefore, synchronization can becompensated according to the delay of each axis, and better synchronization performance can be achieved without complex calculation.

Description

technical field [0001] The invention relates to the technical field of industrial control, in particular to a bus real-time synchronization control device. Background technique [0002] In the field of industrial control, now more and more bus control technology is used. If the bus control wants to achieve a good control effect, two indicators are very important. [0003] 1. How to ensure that although the slave station receives data at different times, it can execute commands at the same time. [0004] 2. How to ensure that the execution interval of each synchronization of the slave station is as consistent as possible with the cycle (for example, the cycle is 100us, and the interval is close to 100us, the better). [0005] The second point above is mainly related to the periodic real-time performance of data sent by the master station. The performance of point 1 will also be affected by the performance of point 2 (if the cycle is inaccurate, synchronization needs to be ...

Claims

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Application Information

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IPC IPC(8): G05B19/042G06F13/28H04L7/00
CPCG05B19/0421G05B19/0423H04L7/0033G06F13/28
Inventor 杨基鹏
Owner 深圳市小步数控有限公司
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