FPGA-based DPA attack resistant AES encryption method

Abstract

The invention discloses an FPGA-based DPA attack resistant AES encryption method, which comprises the steps of: weakening strong correlation between a secret key and dynamic power consumption of an FPGA in an original encryption process through employing a random mask on a plaintext XOR during initial encryption, and effectively resisting a DPA attack for AES encryption; utilizing a redesigned sTable_mask and a mask removing operation, enabling the output encrypted data to accord with a standard AES encryption rule; and storing a plurality of sTable_masks in one ROM, so that table look-up operation logic is simplified. On the aspect of system architecture, a full pipeline design is adopted, and the inter-stage logic complexity is simplified by using a plurality of ROM table lookup modes, so that the maximum working frequency of the system is greatly improved, and the throughput of the system is further improved.

Description

technical field [0001] The invention belongs to the field of password attack and defense, and relates to an FPGA-based AES encryption method against differential power analysis attack. Background technique [0002] In recent years, with the gradual maturity of 5G technology, application scenarios that rely on high real-time characteristics, such as Internet of Vehicles and telemedicine, have gradually emerged. In these scenarios, it is necessary to ensure the safe transmission of data and meet the high throughput and low time requirements of data. To meet the delay requirements, using FPGA to encrypt and decrypt data has become a feasible solution. However, the traditional FPGA-based AES encryption method is vulnerable to differential power analysis (DPA, Differential Power Analysis) attacks, so an FPGA architecture that meets high throughput and low latency and resists DPA attacks is needed. Contents of the invention [0003] Aiming at the deficiencies of the prior art, ...

AI Technical Summary

Problems solved by technology

The traditional FPGA-based AES encryption method is vulnerable to differential power analysis (DPA, Differential Power Analysis) attacks, so an FPGA architecture that meets high-throughput and low-latency anti-DPA attacks is needed

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