A method of converting avalon bus to axi4 bus

Abstract

The application discloses a method for converting an Avalon bus to an Axi4 bus, comprising: when the Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, and outputting corresponding Axi4_st bus data after logically processing the received Avalon_st bus data; When the bus is the Avalon_mm bus, it receives the signal transmitted by each channel of the Avalon_mm bus and stores the signal into asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready, reads the signal from the asynchronous FIFO, and according to the timing of the Axi4 bus The relationship outputs the signal to the corresponding channel of the Axi4 bus. The method can realize the conversion of the Avalon bus to the Axi4 bus without delay and across clock domains, and realizes the work of fast design and matching interface in the cross-platform general design or code transplantation scheme.

Description

Technical field [0001] The present application relates to the field of data conversion technology, and more particularly to a method of AVALON bus transfer AXI4 bus; further involves an apparatus, device, and computer readable storage medium of Avalon bus transfer AXI4 bus. Background technique [0002] The Avalon bus is an internal interconnected bus technology developed by Altera, which can automatically generate without user intervention, which is often used as an ideal inner bus between the system processor and peripherals. At the same time, the Avalon bus has independent addresses, data, and control lines, supports data width within 128 digits, supports synchronous operation, and does not require complex handshake / response mechanisms, so Avalon bus is flexible and widely used. The AXI4 bus is a kind of high-performance, high broadband, low-delayed film, which is the main feature of address / control and data transmission, and it will read and write data channels. Divide, s...

AI Technical Summary

Problems solved by technology

However, this IP can only be used on the Xilinx platform, which has a large delay, and does not support cross-clock domain conversion, so its use is limited

Images