Array substrate and display panel
An array substrate and area technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of reduced capacitance between gates, metal residues, etc., and achieve the effect of ensuring constant capacitance and good flattening
Active Publication Date: 2022-08-05
WUHAN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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Problems solved by technology
[0004] The invention provides an array substrate and a display panel, so as to alleviate the problems of metal residue between gates and reduction of capacitance between gates existing in the current array substrate after metal etching
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[0025] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [up], [down], [front], [rear], [left], [right], [inner], [outer], [side], etc., are only for reference Additional schema orientation. Therefore, the directional terms used are for describing and understanding the present invention, not for limiting the present invention. In the figures, structurally similar elements are denoted by the same reference numerals.
[0026] The present invention aims at the problems of gate metal residue and reduction in capacitance between gates after metal etching in the current display screen technology, which can be alleviated by the embodiments of the present invention.
[0027] like figure 1 As shown, in one embodiment, the present invention provides an array substrate, comprising: a substrate (including a ...
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Abstract
The present invention provides an array substrate and a display panel, the array substrate includes a substrate, a first gate layer, a gate insulating layer, and a second gate layer, wherein: the first gate layer is patterned to form scanning signal lines and a first electrode plate, the second gate is patterned to form reset traces and a second electrode plate, the gate insulating layer is deposited by one or at least two inorganic layers, and the gate layer is The corresponding position of the first electrode plate is provided with a groove, and the second electrode plate is disposed in the groove; due to the relatively large selection of dry etching of the inorganic layer, the gate insulating layer can cover the first gate electrode It can achieve better planarization when the second gate layer is etched, so as to alleviate the problem of metal residues on the edge of the first gate layer during etching of the second gate layer. At the same time, because the gate insulating layer is provided with grooves, the second electrode The plate is arranged in the groove, which can ensure that the capacitance between the first grid and the second grid remains unchanged.
Description
technical field [0001] The present invention relates to the field of display technology, and in particular, to an array substrate and a display panel. Background technique [0002] After the patterning process of the first gate layer of the current array substrate, a steeper edge will be formed, so that the gate insulating layer cannot be flattened when covering the first gate layer, resulting in the etching of the second gate layer. , there is metal residue on the edge of the first gate layer; however, if the thickness of the gate insulating layer is increased to achieve planarization, the capacitance between the first gate layer and the second gate layer will be reduced. [0003] That is, the current array substrate has problems and needs to be improved. SUMMARY OF THE INVENTION [0004] The present invention provides an array substrate and a display panel to alleviate the problems of metal residues between gates and reduction of capacitance between gates after metal et...
Claims
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IPC IPC(8): H01L27/12H01L27/32
CPCH01L27/1237H01L27/124H10K59/1213H10K59/12
Inventor 杨薇薇
Owner WUHAN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD