43results about How to "Improve planarization" patented technology

The invention discloses a polishing pad for solving the problems of nonuniform distribution of polishing liquid and need of further improvement of the polishing speed and the leveling degree in a traditional polishing pad. The polishing pad at least comprises a circular polishing layer; a groove for flowing the polishing liquid is formed in the upper surface of the polishing layer; the groove consists of a peripheral groove and a radial groove; the peripheral groove is a peripheral geometric center symmetry pattern with the circle center of the polishing layer as center; the edges m of the pattern are not fewer than 3; and the radial groove is a straight line or/and a curve scattered from the peripheral direction along the circle center, and has an intersecting point with the peripheral groove. The polishing pad is simple in structure, can enable the polishing liquid to uniformly distribute and flow in a polishing area, keeps uniform concentration of reactants and products in the polishing liquid in the polishing area to the greatest extent, accelerates the polishing speed, and improves the wafer planar degree.

Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

The invention discloses a mask plate, a manufacturing method thereof, a display panel and a display device. According to the mask plate, the manufacturing method thereof, the display panel and the display device, a traditional mask plate is improved, particularly, a notch is formed at the positions where at least part of the side cut surface of each opening of the mask plate intersects with the surface of one side close to a substrate during evaporation, the notches are formed through the chemical etching method or the laser cutting method, the area of the side, close to the substrate, of an opening is made to be larger than the area of the side, away from the substrate, of the opening during evaporation, in this way, the area of the marginal area of an evaporated film on the substrate is increased, the flatness of the marginal area is improved, the possibility that the metal film formed in the later stage breaks due to the fact that a step is too high is avoided, and the yield of products is increased.

The invention provides a method for adding redundant graphics. The method comprises the following steps: dividing a domain into a plurality of subdomains in the same size and calculating an original density value of each subdomain; dividing the subdomains into a plurality of groups and taking the subdomains with the same or similar original density values as one group; selecting the groups in which the redundant graphics need to be added; calculating the sizes of the redundant graphics needing to be added in the subdomains of each group according to the density values; setting a scaling value and scaling each of the redundant graphics in the subdomains of the same group according to the scaling value; calculating the scaled density values of the subdomains; calculating a density difference of the original density values and the scaled density values of the subdomains; and adjusting the sizes of the redundant graphics according to an absolute value of the density difference, wherein the sizes of the redundant graphics are decreased along with the increasing of the absolute value of the density difference. According to the method, the homogeneous density distribution of wafers is ensured; the density distribution difference of the domain and the wafers is reduced, so that the flatness degree is improved.

The present invention provides: a multilayer substrate in which a spacer is selectively disposed in a non-display region without reduction in display quality or productivity of a liquid crystal display device; a production method thereof; and a liquid crystal display panel and a liquid crystal display device each using the multilayer substrate or the production method thereof. The multilayer substrate of the present invention is a multilayer substrate comprising a resin interlayer film and an electrode on a substrate in this order, wherein the multilayer substrate has a depression structure including the resin interlayer film in a surface layer, or a depression structure having a rough bottom surface on the resin interlayer film.

A complex chemical mechanical polishing process for planarizing a structure. The process comprises steps of performing a main polishing process with a first polishing rate, wherein a slurry is provided. An assisted polishing process is then performed to planarizing the structure. The assisted polishing process comprises steps of providing the slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate.

The invention provides an array substrate and a preparation method therefor and a display apparatus. The array substrate comprises an insulating layer; the insulating layer comprises a transparent part and a light shielding part; and the projection of the light shielding part on the substrate of the array substrate covers the projections of a gate line, a source, a drain and a data line on the substrate of the array substrate. Therefore, the light shielding part can replace a conventional black matrix, so that product structure can be simplified and the product thickness can be reduced; and in addition, the dimension of the light shielding part can be smaller than that of the conventional black matrix, so that aperture ratio can be improved.

The invention relates to a stack type package structure and a manufacture method thereof. The method comprises the steps of: forming and curing a first protective layer for covering a first convex block of a first wafer; cutting the first wafer to form a plurality of first crystal particles; forming a second protective layer for covering a second convex block of a second wafer; absorbing the first crystal particles by using a joint through the first protective layer, jointing the first crystal particles on the second wafer; removing the joint, removing part of the first protective layer; cutting the second wafer to form a plurality of second crystals; forming a third protective layer on a base plate; and jointing the first crystal particles and the second crystal particles on the base plate. Therefore, the first protective layer can protect the first convex block, and the first protective layer has the function of increasing the thickness and flattening so as to be beneficial to the absorption of the first crystal particles.

The invention discloses a semiconductor silicon wafer, a flattening method therefor, a preparation method therefor, and a semiconductor device. The flattening method comprises the steps: corroding silicon oxynitride on silicon nitride of an active region in the semiconductor silicon wafer provided with a field oxidation layer through employing hydrofluoric acid solution or the mixed solution of hydrofluoric acid and ammonium fluoride; grinding the surface of the semiconductor silicon wafer through employing the CMP technology, wherein the silicon oxynitride of the semiconductor silicon wafer is corroded; corroding the residual silicon oxynitride on the surface of the ground semiconductor silicon wafer through employing hot phosphoric acid, and obtaining semiconductor silicon chip. Therefore, the method enables all silicon oxynitride in the active region to be corroded before the CMP technology, prevents the incomplete grinding of the silicon oxynitride in the active region of the semiconductor silicon wafer in a smaller area from causing the incomplete corrosion of silicon nitride in a region where there is the residual silicon oxynitride, guarantees that the surface of the active region in the finally obtained semiconductor silicon wafer is completely exposed, and improves the flattening degree of the semiconductor silicon wafer.

The invention discloses a chip flattening method. The chip flattening method includes: providing a silicon substrate and forming a metal layer with an initial thickness on the silicon substrate; grinding the metal layer by a chemical mechanical grinding technology with first pressing force and a first rotary table rotation speed so as to enable the metal layer to be changed from the initial thickness to a first target thickness; grinding the metal layer by the chemical mechanical grinding technology with second pressing force and a second rotary table rotation speed so as to enable the metal layer to be changed from the first target thickness to a second target thickness, wherein the second pressing force is smaller than the first pressing force, and the second rotary table rotation speed is identical to the first rotary table rotation speed. The chip flattening method has the advantages that the metal layer is grinded at the high speed with the larger pressing force and then grinded at the high speed with the smaller pressing force, overall flattening of the surface of the silicon substrate can be improved, flattening of the surface of a chip can be improved, and thereby yield of a semiconductor device can be increased. According to the chip flattening method, the metal layer can be grinded at the high speed with the smaller pressing force and then grinded at the same speed with the larger pressing force.

The invention provides a grinding head and chemical mechanical grinding equipment. The grinding head comprises a main body component for bearing wafers, a connecting component, a metal clamping ring and a ground lead, wherein the connecting component is fixed to the main body component; the connecting component comprises a conductive material; the clamping ring is arranged on the outer circumference of the main body component; the clamping ring is made of a conductive material; and a metal material of the connecting component is electrically connected with the clamping ring through the electrical connection line. Through the electrical connection line, charges unevenly distributed on the wafers caused by by-products generated by reaction during grinding can be conducted to the ground end,therefore, the planarization defect caused by uneven charges is avoided, and the planarization degree is increased.

The invention provides a polishing layer, a polishing pad with the polishing layer and a preparation method of the polishing layer, and relates to the technical field of polishing of chemical mechanical planarization treatment. The preparation method comprises the following steps that prepolymer of bifunctional or polyfunctional isocyanate in component A and a multi-component mixture of a hollow microsphere in component B and a curing agent in component C are prepared; forming by pouring is carried out, specifically, the multi-component mixture is poured into a mould cavity and subjected to leveling gelation; heating and solidifying are carried out, specifically, a mould loading a gelatinous ternary mixture is heated and solidified, to obtain a pouring body; and when the temperature is lowered to a predetermined temperature T, the heat preservation and slice cutting are performed, and the horizontal cutting rate V of a cutter relative to the pouring body during slice cutting meets: 8cm/s <= V<= 20 cm/s.

On a glass substrate of a liquid crystal display device, electrode parts to which metallic electrodes (bumps) of an IC circuit are connected from an upper part are formed. The electrode parts are formed by opening an interlayer dielectric film at parts corresponding to metal wiring and forming land shaped electrode pads in the opening parts. In this invention, the planar forms of the electrode pads are smaller than the opening parts of the interlayer dielectric film. Thus, the planarization of the peripheral surfaces around the electrode parts is improved. Accordingly, integrated circuit devices (IC) or semiconductor chips can be connected with high reliability.