Chip flattening method

Abstract

The invention discloses a chip flattening method. The chip flattening method includes: providing a silicon substrate and forming a metal layer with an initial thickness on the silicon substrate; grinding the metal layer by a chemical mechanical grinding technology with first pressing force and a first rotary table rotation speed so as to enable the metal layer to be changed from the initial thickness to a first target thickness; grinding the metal layer by the chemical mechanical grinding technology with second pressing force and a second rotary table rotation speed so as to enable the metal layer to be changed from the first target thickness to a second target thickness, wherein the second pressing force is smaller than the first pressing force, and the second rotary table rotation speed is identical to the first rotary table rotation speed. The chip flattening method has the advantages that the metal layer is grinded at the high speed with the larger pressing force and then grinded at the high speed with the smaller pressing force, overall flattening of the surface of the silicon substrate can be improved, flattening of the surface of a chip can be improved, and thereby yield of a semiconductor device can be increased. According to the chip flattening method, the metal layer can be grinded at the high speed with the smaller pressing force and then grinded at the same speed with the larger pressing force.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing technology, in particular to a chip planarization method. Background technique [0002] The rapid development of computer, communication and network technology has higher and higher requirements on semiconductor devices. Semiconductor devices are constantly developing in the direction of high speed, high integration, high density and high performance, resulting in the continuous shrinking of their feature size and the continuous reduction of metal interconnection. The number of interconnected wiring layers continues to increase. In the three-dimensional structure of multilayer wiring, it is required not only to planarize the surface of the entire silicon chip including all chips (global planarization), but also to planarize the surface of each chip. Because whether it is the uneven surface of the silicon wafer or the uneven surface of the chip, it will have a negative i...

AI Technical Summary

Problems solved by technology

However, during the entire grinding process, if the silicon wafer is ground with a large down force, it is easy to produce dish-shaped depressions on the silicon wafer, which reduces the global planarization of the silicon wafer surface, and more importantly, it is difficult to planarize the chip surface on the silicon wafer. good control

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