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An accelerator management architecture, method and accelerator interface controller

A technology of interface controller and accelerator, applied in bus network, data exchange through path configuration, electrical components, etc., can solve inefficiency, increase DSP load, increase wireless communication system delay, wireless communication system bandwidth requirements, capacity requirements, etc. problem, to achieve the effect of reducing delay and reducing DSP load

Active Publication Date: 2022-03-25
上海金卓科技有限公司
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  • Description
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  • Application Information

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Problems solved by technology

However, the DSP needs to manage the data processing of each accelerator, which increases the DSP load. At the same time, the data needs to be continuously transmitted between the accelerator and the DSP or MEM, which is inefficient, and increases the delay of the wireless communication system, the bandwidth requirements of the wireless communication system, and Capacity requirements of wireless communication system for MEM

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  • An accelerator management architecture, method and accelerator interface controller
  • An accelerator management architecture, method and accelerator interface controller
  • An accelerator management architecture, method and accelerator interface controller

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Embodiment 1

[0031] image 3 This is a schematic structural diagram of an accelerator management architecture provided by Embodiment 1 of the present invention, and the embodiment of the present invention can be applied to the case where the accelerator is flexibly scheduled to implement different protocol processing or algorithm processing flows in wireless communication.

[0032] like image 3 As shown, the management architecture includes: a DSP 110, a memory 120, a bus 130, at least one accelerator 140, and an accelerator interface controller 150 corresponding to the accelerators 140 one-to-one; wherein, the DSP 110 and the memory 120 are respectively connected to the bus 130; 140 are respectively connected to the bus 130 through the corresponding accelerator interface controllers 150 .

[0033] The DSP 110 is used to pre-store the specified task and the task description information corresponding to the subtasks in the specified task in the memory 120, and to the accelerator interface...

Embodiment 2

[0046] Figure 4 It is a schematic structural diagram of an accelerator management architecture provided by Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution. The technical solution in this embodiment may be different from each of the above one or more embodiments. Combining options.

[0047] like Figure 4 As shown, the management architecture includes: a DSP 110, a memory 120, a bus 130, at least one accelerator 140, and an accelerator interface controller 150 corresponding to the accelerators 140 one-to-one; wherein, the DSP 110 and the memory 120 are respectively connected to the bus 130; 140 are respectively connected with the bus 130 through the corresponding accelerator interface controller 150.

[0048] The DSP 110 is used to pre-store the specified task and the task description information corresponding to the subtasks in the specified task in the memory 120, and to the accelerator interface controller cor...

Embodiment 3

[0060] Figure 5 This is a flowchart of an accelerator management method provided in Embodiment 3 of the present invention, and the method is applied to an accelerator interface controller. like Figure 5 As shown, the method of the embodiment of the present invention specifically includes:

[0061] Step 210: Acquire the task description information and the current subtask in the specified task from the data signal processor DSP or from the memory, and parse the task description information.

[0062] Step 220, obtain the parsed task description information and the current subtask from the corresponding accelerator interface controller through the accelerator, execute the current subtask according to the parsed task description information, and send the execution result to the next accelerator that performs the next task, and controlling the startup of the next accelerator based on the task description information and the accelerator interface controller corresponding to the ...

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Abstract

The embodiment of the invention discloses an accelerator management framework, a method and an accelerator interface controller. The architecture includes a data signal processor DSP, a memory, a bus, an accelerator, and an accelerator interface controller corresponding to the accelerator; wherein, the DSP pre-stores the task description information corresponding to the specified task and the subtasks in the specified task in the memory, and sends the information to the execution The accelerator interface controller corresponding to the accelerator of the first subtask sends the corresponding task description information and the current subtask; the accelerator interface controller parses the task description information; the accelerator obtains the parsed task description information and the current subtask from the corresponding accelerator interface controller The task obtains data according to the task description information to execute the current subtask, sends the execution result to the next accelerator executing the next subtask, and sends a start message and the address of the next subtask to the next accelerator. It can reduce the delay, reduce the DSP load, and flexibly call the accelerator at the same time.

Description

technical field [0001] Embodiments of the present invention relate to the field of wireless communication technologies, and in particular, to an accelerator management architecture, a method, and an accelerator interface controller. Background technique [0002] In a wireless communication system, in order to realize the rapid transmission of communication data, accelerators of multiple algorithms are usually integrated to jointly complete each protocol processing and algorithm processing flow. [0003] In the prior art, there are generally two ways of accelerator management architecture: figure 1 It is the first connection diagram of the accelerator management architecture in the prior art, such as figure 1 As shown in the figure, the accelerators processing various protocols and algorithms in the wireless communication system are connected in a hardened manner. All accelerators are hardened and connected to each other. Only the accelerator at the head is connected to the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L69/18H04L69/22H04L12/40
CPCH04L69/18H04L69/22H04L12/40
Inventor 郭晗
Owner 上海金卓科技有限公司
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