Clock processing circuit in chip debugging mode and clock processing method thereof

A technology for processing circuits and debugging modes, which is applied in electrical digital data processing, software testing/debugging, error detection/correction, etc., and can solve problems that affect the chip process and chip operating program development efficiency, so as to improve development efficiency , Optimize the effect of the development process

CN111459785APending Publication Date: 2020-07-28BEIJING TONGFANG MICROELECTRONICS
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2020-07-28

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Abstract

The invention provides a clock processing circuit in a chip debugging mode and a clock processing method thereof. The clock processing circuit comprises a first selector, a second selector, a latch and a logic AND gate, the first selector is connected with the second selector, the second selector is connected with the latch, and the latch is connected with the logic AND gate. In a chip debugging mode, a chip carries out special processing on the system clock, a system clock signal can be turned over normally, moreover, after the chip enters the dormant state, the system clock does not stop dueto system dormancy, the chip and a computer can normally send and receive the signal for confirming the connection state, the chip can still work normally without exiting the debugging mode, the problem that the chip running program is interrupted in the debugging process is solved, the chip running program development process is optimized, and the development efficiency of the chip running program is improved.
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Description

Technical field

[0001] The present invention relates to the technical field of integrated circuit digital design, and in particular to a clock processing circuit in a chip debugging mode and a clock processing method thereof. Background technique

[0002] During the development of the chip operating program, developers need to continuously debug the chip operating program. At this time, the chip operating mode needs to be switched to the debugging mode, and the chip operating program may contain commands to make the chip system sleep. When the chip enters the sleep state, stopping the system clock will cause the chip to exit the debugging mode, and the program debugging process is interrupted, so that the program following the sleep command cannot be debugged.

[0003] Such as figure 1 Shown is the working principle diagram of the existing chip debugging. In the chip debugging working principle diagram, Chip is the chip, which contains the clock processing circuit CLK Circuit; Uli...

Examples

Embodiment Construction

[0019] See figure 2 , The structure diagram of the clock processing circuit in the chip debugging mode implemented in the present invention. In the structure of the clock processing circuit in the chip debugging mode, the clock processing circuit includes a first selector MUX1, a second selector MUX2, a latch and a logical AND gate AND, the first selector MUX1 is connected to the second selector MUX2 , The second selector MUX2 is connected to the latch Latch, and the latch Latch is connected to the logic AND gate AND.

[0020] See figure 2 When the clock processing circuit works, firstly, the external clock signal CLK is given to the clock processing circuit, and the system sleep signal sfr_idlesleepcon_sleepen, the system deep sleep signal sfr_idledbgcon_dbgsleepen, and the system debug signal sfr_idledbgcon1_en are all set to 0 through the external configuration register; then, The system sleep signal sfr_idlesleepcon_sleepen is input to the first selector, and the system dee...