Overlay alignment mark and overlay error measurement method

Abstract

The invention provides an overlay alignment mark in a patterned wafer, and an overlay error measurement method, wherein the wafer has a lower layer pattern in a first layer and an upper layer patternin a second layer above the first layer. The overlay alignment mark comprises: a first pattern used as a part of the lower layer pattern and including a pair of physical features formed in the first layer; and a second pattern used as a part of the upper layer pattern and including two pairs of hollow-out features formed on the second layer, wherein the geometric center connecting line of one pairof hollowed-out features and the geometric center connecting line of the other pair of hollowed-out features extend in two orthogonal directions respectively, and the orthographic projection of the pair of entity features on the wafer is at least partially overlapped with the orthographic projection of the corresponding pair of hollowed-out features in the two pairs of hollowed-out features on the wafer.

Description

technical field [0001] The present disclosure relates to the field of semiconductor manufacturing and inspection, and more particularly to an overlay alignment mark (especially for SEM imaging) and an overlay error measurement method. Background technique [0002] In the semiconductor device manufacturing technology, the mask pattern on the mask plate is usually transferred to the photoresist layer on the surface of the wafer by photolithography process. A photolithography process typically includes steps such as photoresist coating, masking, exposure, and development. With the continuous improvement of the integration level of semiconductor devices, the feature size of the devices is continuously reduced, and the process is becoming more and more complex. In order to achieve good device performance, each layer of photolithographic patterns has strict feature size requirements. The way to reduce the size of semiconductor devices usually includes increasing the layout densit...

AI Technical Summary

Problems solved by technology

However, in practical applications, especially in specific occasions (such as the development process of the device or in the later error checking process), the situation that the special overlay measurement mark may be missing may occur, which makes the overlay error measurement method of the related technology invalid

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