FPGA remote upgrading method for 5G distributed base station RRU equipment and terminal
A distributed base station and remote upgrade technology, applied in the FPGA remote upgrade method and terminal field of 5G distributed base station RRU equipment, can solve problems such as labor waste and low efficiency, reduce operation and maintenance costs, reduce hardware costs, and improve upgrade efficiency Effect
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Embodiment 1
[0069] Please refer to figure 1 , Embodiment 1 of the present invention is:
[0070] A 5G distributed base station RRU device FPGA remote upgrade method, comprising steps:
[0071] S1. Run according to the basic version program in the first storage space;
[0072] That is, when the RRU device leaves the factory, the first upgrade status value 1 is written into the EEPROM, and the basic version program is pre-programmed in the first storage space. After the distributed base station is set up and activated, the RRU device starts, and the FPGA reads from the first storage space by default. Take the basic version program, after the FPGA is started, read the upgrade status value of the EEPROM module as the first upgrade status value 1, then the FPGA does not perform the program upgrade, runs according to the basic version program in the first storage space, and the device works normally;
[0073] S2. Receive the upgrade instruction and the first upgrade program remotely sent by t...
Embodiment 2
[0087] Please refer to figure 2 and image 3 , the second embodiment of the present invention is:
[0088] A 5G distributed base station RRU equipment FPGA remote upgrade terminal 1, including a memory 3, a processor 2, and a computer program stored on the memory 3 and operable on the processor 2, and the above-mentioned embodiment is realized when the processor 2 executes the computer program Step S1 to step S4 in one.
[0089] like image 3 As shown, in this embodiment, the processor 2 is equivalent to the FPGA6 in the RRU5, and the memory 3 is any storage device in the RRU5. The storage device of the computer program of steps S1 to S4 is composed.
[0090] In this embodiment, the overall architecture between BBU4 and RRU5 is as follows image 3 As shown, corresponding to the analog switch 7, EEPROM8, latch 11 and reset module 12 in the first embodiment above, wherein, FLASH19 is the first storage space for storing the basic version program, FLASH210 is the second stor...
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