Method, device and chip for reducing core size of nonvolatile flash memory

A non-volatile, flash memory technology, applied in the direction of instruments, electrical digital data processing, electrical components, etc., can solve problems affecting device performance, reduce the overall area, avoid the increase of leakage current, and reduce the core size.

Active Publication Date: 2020-09-04
XTX TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a method, device and chip for reducing the core size of non-volatile flash memory, aiming to

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  • Method, device and chip for reducing core size of nonvolatile flash memory
  • Method, device and chip for reducing core size of nonvolatile flash memory
  • Method, device and chip for reducing core size of nonvolatile flash memory

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[0029] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present application.

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Abstract

The invention discloses a method, a device and a chip for reducing the core size of a nonvolatile flash memory. The method comprises the following steps: judging whether adjacent well regions with consistent working voltage exist on a chip or not, and removing the distance between the adjacent well regions with consistent working voltage if the adjacent well regions with consistent working voltageexist, so that the adjacent well regions with consistent working voltage are merged together; according to the technical scheme, the total area of a specific module region of the chip can be greatlyreduced, and the width-to-length ratio of the mos device does not need to be reduced, so that the problems of leakage current increase and breakdown voltage reduction caused by reduction of the width-to-length ratio of the mos device are avoided.

Description

technical field [0001] The invention relates to the field of IC technology manufacturing, in particular to a method, device and chip for reducing the core size of a non-volatile flash memory. Background technique [0002] With the increasing integration of IC chips, the overall area of ​​the chip becomes particularly important for the cost of chip manufacturing. In order to manufacture more mos devices on the same area, we need to maximize the performance of the device without losing device performance. Under the premise, try to reduce the size of the mos components used. [0003] The traditional device miniaturization method, such as the miniaturization method of the MOS tube, mainly reduces the width (width) and length (length) of the MOS tube in the same proportion, but with the shrinking of the channel length of the MOS tube, the MOS tube is facing serious problems. Leakage (leakage loss) leakage increases, breakdown (breakdown) voltage decreases and other device perfor...

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Application Information

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IPC IPC(8): G06F30/392H01L27/02
CPCG06F30/392H01L27/0207
Inventor 张柱定
Owner XTX TECH INC
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