Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method, device and chip for reducing core size of nonvolatile flash memory

A non-volatile, flash memory technology, applied in the direction of instruments, electrical digital data processing, electrical components, etc., can solve problems affecting device performance, reduce the overall area, avoid the increase of leakage current, and reduce the core size.

Active Publication Date: 2020-09-04
XTX TECH INC
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a method, device and chip for reducing the core size of non-volatile flash memory, aiming to solve the problem that the existing method of improving chip area utilization by shrinking the size of the device affects the performance of the device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method, device and chip for reducing core size of nonvolatile flash memory
  • Method, device and chip for reducing core size of nonvolatile flash memory
  • Method, device and chip for reducing core size of nonvolatile flash memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0030] It should ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method, a device and a chip for reducing the core size of a nonvolatile flash memory. The method comprises the following steps: judging whether adjacent well regions with consistent working voltage exist on a chip or not, and removing the distance between the adjacent well regions with consistent working voltage if the adjacent well regions with consistent working voltageexist, so that the adjacent well regions with consistent working voltage are merged together; according to the technical scheme, the total area of a specific module region of the chip can be greatlyreduced, and the width-to-length ratio of the mos device does not need to be reduced, so that the problems of leakage current increase and breakdown voltage reduction caused by reduction of the width-to-length ratio of the mos device are avoided.

Description

technical field [0001] The invention relates to the field of IC technology manufacturing, in particular to a method, device and chip for reducing the core size of a non-volatile flash memory. Background technique [0002] With the increasing integration of IC chips, the overall area of ​​the chip becomes particularly important for the cost of chip manufacturing. In order to manufacture more mos devices on the same area, we need to maximize the performance of the device without losing device performance. Under the premise, try to reduce the size of the mos components used. [0003] The traditional device miniaturization method, such as the miniaturization method of the MOS tube, mainly reduces the width (width) and length (length) of the MOS tube in the same proportion, but with the shrinking of the channel length of the MOS tube, the MOS tube is facing serious problems. Leakage (leakage loss) leakage increases, breakdown (breakdown) voltage decreases and other device perfor...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F30/392H01L27/02
CPCG06F30/392H01L27/0207
Inventor 张柱定
Owner XTX TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com