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A centralized-distributed mixed organization of shared memory for neural network processing

A technology of processor and local memory, applied in biological neural network model, input/output process of data processing, neural architecture, etc., can solve problems such as memory bank conflicts and increased performance problems

Active Publication Date: 2020-09-04
ALIBABA GRP HLDG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Many memory architectures exist that provide cross-channel data processing and computation, but these architectures are deficient for several reasons, such as unacceptable increases in memory access latency, bank conflict issues, performance issues, etc.

Method used

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  • A centralized-distributed mixed organization of shared memory for neural network processing
  • A centralized-distributed mixed organization of shared memory for neural network processing
  • A centralized-distributed mixed organization of shared memory for neural network processing

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Embodiment Construction

[0019] The following description refers to the accompanying drawings, wherein like numerals in different drawings indicate the same or similar elements unless otherwise indicated. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with relevant aspects of the invention as set forth in the appended claims.

[0020] refer to figure 1 , which is a schematic diagram showing an exemplary centralized shared memory storing data to be exchanged between SIMD lanes. The centralized shared memory architecture includes multiple processing units (e.g., figure 1 Processing unit 0, processing unit 1, processing unit N) and memory blocks are shown.

[0021] These processing units can be configured to provide the same or different functions and be connected to the same memory blocks (e.g., figure 1 in memory). Each pr...

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Abstract

The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memoryconfigured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from U.S. Provisional Application No. 62 / 610,098, filed December 22, 2017, and U.S. Patent Application No. 16 / 201,904, filed November 27, 2018, the entire contents of which are incorporated by reference here. Background technique [0003] Deep neural network algorithms involve massive matrix computations, which often result in hardware architectures involving very wide single-instruction multiple-data (SIMD) processing units and large on-chip storage. Due to the nature of deep learning, different SIMD channels need to exchange data from time to time. There are many memory architectures that provide cross-channel data processing and computation, but these architectures are deficient for several reasons, such as unacceptable increases in memory access latencies, bank conflict issues, performance issues, and the like. Contents of the invention [0004] The present disclos...

Claims

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Application Information

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IPC IPC(8): G06F3/06G06F13/28G06N3/04G06N3/10
CPCG06F13/4027G06N3/063G06F15/163G06F3/0604G06F3/0659G06F3/0673G06F2213/28G06F13/28G06F13/4282G06F2213/0026G06N3/08
Inventor 韩亮蒋晓维陈健
Owner ALIBABA GRP HLDG LTD