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Calculation circuit

A computing circuit and circuit technology, applied in the field of computing circuits that perform product-sum operations, can solve the problems of increasing quantity and power consumption, wasting circuit scale and power consumption, and large noise components, and achieve the effect of reducing area and power

Pending Publication Date: 2020-09-04
NTT ELECTORNICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, an increase in the number of bits increases the number of elements and power consumption, but the lower bits accurately calculated by the multiplying circuit 1000-n are deleted by the bit matching circuit 1002 as bits having a large noise component
[0015] Therefore, the multiplying circuit 1000-n used in the conventional product-sum operation circuit includes a circuit for accurately calculating the lower bit value, which is invalidated by the bit matching circuit 1002 because of a large noise component, so wasted For accurate calculation of the area of ​​the lower bit value of the circuit and the power consumed by the circuit
Especially when the number of bits of data or the number of bits of coefficients is increased to improve the accuracy of a digital signal processing system, circuit scale and power consumption are wasted

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0038] Hereinafter, embodiments of the present invention will be described with reference to the drawings. figure 1 is a block diagram showing the arrangement of an arithmetic circuit according to the first embodiment of the present invention. The operation circuit of this embodiment receives M (M is an integer of 2 or greater) data sets X[m] (m=1, . . . , M) and N (N is an integer of 2 or greater) coefficients c[n] (n=1, . . . , N). Each data set X[m] (m=1, . . . , N) includes N data x[m, n] (n=1, . . . , N). Note that the data x[m,n] and the coefficient c[n] are respectively two's complement binary numbers representing signed fixed-point numbers. Let x_scale be the number of decimal places for each data x[m,n] and c_scale be the number of decimal places for each coefficient c[n].

[0039] figure 1 The arithmetic circuit shown in calculates and outputs M product-sum operation values ​​z[m] (m=1, . . . , M) for the above-mentioned inputs. Each of the product-sum operati...

no. 2 example

[0083] Next, a second embodiment of the present invention will be described. Figure 7 is a block diagram showing the arrangement of an arithmetic circuit according to a second embodiment of the present invention. Figure 7 The arithmetic circuit shown in receives: M (M is an integer of 2 or greater) complex numbers X[m] (m=1, . . . , M), each of which is divided into real parts a value x_real[m] and an imaginary part value x_imag[m] (m=1, . . . , M); and a complex coefficient C, which is divided into a real part value c_real and an imaginary part value c_imag. Note that the data x[m, n] (m=1,..., M, n=1,..., N) is a signed value (expressed by a two's complement binary number) that can take negative values value). Let x_scale be the number of decimal places of the real part value x_real[m] and the imaginary part value x_imag[m] of each complex number X[m] (m=1,...,M), and let c_scale be the number of complex coefficients C The number of decimal places for the real part valu...

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Abstract

This calculation circuit is provided with: a LUT generation circuit (1) that, when coefficients c[n] (n=1,..., N) are divided into pairs, outputs a value calculated for each of the pairs; and a distribution calculation circuit (2-m) that calculates, for each pair of M pairs of data pieces x[m, n] in parallel, a product-sum calculation value z[m] obtained by multiplying, respectively with the coefficients c[n], data pieces x[m, n] in a data set X[m] (m=1,..., M) including the M pairs and by summing the multiplied values. The distribution calculation circuit (2-m) is formed of: a plurality of binomial distribution calculation circuits that calculate binomial product-sum calculation values for each pair, on the basis of a value obtained by dividing N data sets x[m, n] corresponding to the distribution calculation circuit into pairs, a value obtained by dividing the coefficients c[n] into pairs, and the value calculated by the LUT generation circuit (1); a summing circuit that sums the calculated values; and a digit adjustment circuit that adjusts the number of digits after a decimal point in the summed result to a predetermined number of digits after a decimal point.

Description

technical field [0001] The present invention relates to an operation circuit for digital signal processing, and more particularly, to an operation circuit for performing product-sum operation. Background technique [0002] A main operation in digital signal processing is a product-sum operation that multiplies digital signal data expressed as fixed-point binary numbers by coefficients also expressed as fixed-point binary numbers and sums the products (see Non-Patent Document 1). Figure 11 The arrangement of a general product-sum operation circuit is shown. [0003] Figure 11 The product-sum operation circuit shown in receives N data x[n] (n=1,...,N) and coefficients c[n] (n=1,...,N) respectively represented by binary numbers . Each data x[n] is a fixed-point binary number, and the number of decimal places (the width of bits after the decimal point) is x_scale. Also, each coefficient c[n] is a fixed-point binary number, and the number of decimal places is c_scale. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/10G06F7/57
CPCG06F17/10G06F7/5443G06F7/5324
Inventor 川合健治粟田亮武井和人饭塚公昭
Owner NTT ELECTORNICS CORP