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3d NAND flash memory and its operation method

A flash memory and 3D technology, applied in the programming method of 3D NAND flash memory and the field of 3D NAND flash memory, can solve the problem of increasing writing time

Active Publication Date: 2021-08-31
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A conventional solution to the above problem is to add a pre-pulse phase before the verify phase, but this increases the write time

Method used

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  • 3d NAND flash memory and its operation method
  • 3d NAND flash memory and its operation method
  • 3d NAND flash memory and its operation method

Examples

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Embodiment Construction

[0012] The pre-pulse phase is included in Incremental Stepped Pulse Programming (ISPP) of three-dimensional (3D) NAND flash memory. The pre-pulse phase of ISPP turns on the unselected upper select gate to reduce the channel potential difference, which increases the writing time of 3D NAND flash memory.

[0013] In order to reduce the writing time of 3D NAND flash memory, figure 1 is a schematic diagram of a programming process 10 for 3D NAND flash memory according to an embodiment of the present invention. The 3D NAND flash memory may include a plurality of bit lines, wherein the bit lines include a plurality of word line (WL) layers. The programming process 10 for 3D NAND flash includes the following steps:

[0014] Step 102: start.

[0015] Step 104: Program the selected word lines of the unselected bit lines of the 3D NAND flash memory.

[0016] Step 106: Perform a first verification process on the selected word line using at least a verification voltage.

[0017] Step...

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Abstract

A programming method for incremental step pulse programming (ISPP) of a three-dimensional (3D) NAND flash memory comprises: programming a selected word line of an unselected bit line of the 3D NAND flash memory; selecting a word line to perform a first verification process; determining whether a first verification voltage for the first verification process of the selected word line is higher than a default voltage; and when the first verification voltage is higher than the default voltage , removing the pre-pulse phase of the ISPP; wherein, the first verification voltage is a verification voltage immediately after the first verification process.

Description

technical field [0001] The present invention relates to a programming method for three-dimensional (3D) NAND flash memory and 3D NAND flash memory, and more particularly, to a programming method for 3D NAND flash memory and 3D NAND flash memory capable of reducing writing time and power consumption of 3D NAND flash memory. Background technique [0002] In order to control the threshold voltage and implement storage of multiple data of the NAND flash memory in a write operation, an incremental step pulse programming (ISPP) technique is adopted. The ISPP technique is configured to interleave program verify operations with threshold voltages between two program operations. The storage cells of the NAND flash memory that pass the program verification operation are prohibited from programming; the storage cells of the NAND flash memory that fail the program verification operation occur before the ISPP technology. The ISPP technique includes a precharge phase and a programming ph...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10G11C16/34G11C16/08G11C16/04
CPCG11C16/10G11C16/3404G11C16/08G11C16/0483G11C16/3459G11C11/5628G11C16/0433G11C16/24G11C16/30G11C16/3436
Inventor 刘红涛黄德佳魏文喆黄莹
Owner YANGTZE MEMORY TECH CO LTD
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