Self-adaptive turn-off two-stage sensitive amplification circuit

Abstract

The invention discloses a self-adaptive turn-off two-stage sensitive amplification circuit. The circuit comprises a first NMOS transistor, a second NMOS transistor, a first-stage sense amplifier, a second-stage sense amplifier and an adaptive feedback circuit. The adaptive feedback circuit comprises an exclusive-OR gate, an OR gate and a delay chain. When the two differential input signals are input into the two-stage sensitive amplifying circuit for amplification, the differential input signals are amplified. The adaptive feedback circuit controls the first-stage sensitive amplifier and the second-stage sensitive amplifier to be turned on; the first-stage sensitive amplifier and the second-stage sensitive amplifier accelerate amplification and output of signals step by step, and after thesignals amplified and output by the two-stage sensitive amplifier circuit reach recognizable numerical level, the self-adaptive feedback circuit controls the first-stage sensitive amplifier and the second-stage sensitive amplifier to be turned off; the static random access memory has the advantages of high amplification speed and low power consumption, and can have high data reading speed and lowpower consumption at the same time.

Description

technical field [0001] The invention relates to a sensitive amplifying circuit, in particular to a two-stage sensitive amplifying circuit with adaptive shutdown. Background technique [0002] The sense amplifier is an important circuit of the SRAM (Static Random Access Memory, SRAM), and its function is mainly to amplify and output the differential data of the bit line pairs of the storage array in the SRAM. Usually, in order to maintain the storage density of the memory array, the number of memory cells mounted on each bit line will be relatively large, up to 64 or 128, and some even reach 256, resulting in tens of femtofam of the load capacitance of each bit line. (fF), and even hundreds of flyaways. However, the read current of the SRAM is small. If ordinary logic circuits are used, it is difficult to realize the rail-to-rail output of the differential data of the bit line pair in a short time, but the sense amplifier can effectively solve this problem. [0003] However...

AI Technical Summary

Problems solved by technology

However, the amplification process of the current-type latching sensitive amplifier is from the voltage difference to the current difference, and then back to the voltage difference. The amplification process is more complicated, so its amplification speed is relatively slow, and the data output speed is slow.

[0005] In order to solve the above problems, the author Nambu H et al. proposed a current mirror sensitive amplifier at the International Solid-State Circuit Conference "International Solid-State Circuit Conference (ISSCC)", which can amplify and output a very small read current, not only The amplification speed is fast, and the output data accuracy is high, but because the current mirror needs bias current, it consumes more power consumption than the latch-type sense amplifier, and the power consumption will be relatively high

And Lai Y-Ch et al., in the magazine "IEEE Trans. Circuits Syst. II, Exp. Briefs", proposed an improved current mirror sense amplifier, which effectively reduces the static power consumption of the sense amplifier, but its Zoom in slowly

Similarly, Sharifkhani M et al., in the journal "IEEE Trans.Very Large Scale Integration", proposed a hybrid sensitive amplifier circuit, which simultaneously mixes voltage-type and current-type latch sensitive amplifier circuits, which can almost achieve " 0" quiescent current, the power consumption is very low, but its amplification speed is relatively slow

[0006] The above-mentioned sensitive amplifying circuit technologies can effectively improve the performance of the entire SRAM, but they are either relatively slow, making the data reading speed of the SRAM slow, or consume more power consumption, making the SRAM high power consumption

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