A method and device for scheduling ultra-high-order single-cycle packets

Abstract

The invention discloses a method and device for ultra-high-order single-cycle message scheduling. The invention includes the first step: extracting the key path of its message scheduling; the second step: adopting a distributed and hierarchical design method to evaluate and build step by step VC arbiter module-level implementation scheme; the third step: adopt the distributed and hierarchical design method to evaluate and construct the port arbitrator module-level implementation scheme step by step; the fourth step: generate the multi-level VC arbitrator corresponding to each input port The port arbitration request of each output port is connected with the arbitration permission output by the multi-stage port arbiter corresponding to each output port; the fifth step: each arrives at the router m x n The packets dispatched from the input port of the sub-switch are output to its output port. The present invention decomposes the ultra-high-order message scheduling function into multi-level independent, asynchronously working low-order arbitrator cascaded scheduling at a relatively small hardware cost, so that its critical path can meet the timing requirements of a specific clock frequency .

Description

technical field [0001] The invention relates to a router message scheduling method, in particular to an ultra-high-order single-cycle message scheduling method and device for constructing a high-performance computing (HPC) (High Performance Computing) interconnected network. Background technique [0002] With the continuous improvement of the performance of microprocessors and memory, the interconnection network connecting millions of computing nodes and storage devices has become a key factor restricting the performance and even the success of high-performance computing systems. Under the scalable multiprocessor architecture, the interconnect network directly determines the remote memory access latency and bandwidth, and thus plays a decisive role in system performance. With the continuous increase of system scale, the problem of low energy efficiency of interconnection network has become the most important technical challenge to realize exascale computing. Low-level inter...

AI Technical Summary

Problems solved by technology

Since both QoS and adaptive routing deadlock-free flow control are implemented using the VC mechanism, the order of packet scheduling increases rapidly, while the complexity of the traditional packet scheduling algorithm is O ( N 2 ), it is difficult to meet the high-performance scheduling requirements of commercial routers ( N is the number of packet arbitration requests)

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