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Parallel layer distribution method based on through hole perception under super-large-scale integrated circuit

A technology of large-scale integrated circuits and distribution methods, which is applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve the problems of increasing the line network and increasing the running time of the layer distribution algorithm, and achieve the goal of reducing the number of through holes and improving efficiency Effect

Active Publication Date: 2020-09-29
FUZHOU UNIV
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  • Application Information

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Problems solved by technology

In addition, with the increasing scale of integrated circuits, the number of nets to be processed has increased significantly, and the increase in the running time of the layer allocation algorithm has become an important constraint factor that limits the efficient design of routing solutions

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  • Parallel layer distribution method based on through hole perception under super-large-scale integrated circuit
  • Parallel layer distribution method based on through hole perception under super-large-scale integrated circuit
  • Parallel layer distribution method based on through hole perception under super-large-scale integrated circuit

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Embodiment Construction

[0044] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0045] The present invention provides a parallel layer allocation method based on through-hole perception under VLSI, comprising the following steps:

[0046] Step S1, via-dominated layer allocation stage:

[0047] Divide the wiring area, divide the line network that can be wired in parallel, and carry out the parallel wiring of the layer allocation based on the principle of the least number of through holes;

[0048] Step S2, negotiation-based via-aware layer allocation stage:

[0049] Sorting, dismantling, and rewiring the illegal nets appearing in the parallel wiring scheme of step S1 in an iterative manner until there is no illegal net;

[0050] Step S21, sorting the illegal wire nets appearing in the parallel wiring scheme of step S1;

[0051] Step S22, divide the wiring area for the illegal wire net, divide the wire net that can ...

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Abstract

The invention relates to a parallel layer distribution method based on through hole perception under a super-large-scale integrated circuit. According to the method, a parallel strategy based on region division is provided, the load of each region can be balanced by sensing the number of line networks of each region, and thus the efficiency of the parallel strategy is improved; according to the method, a through hole optimization strategy based on wire network equivalent wiring scheme perception is provided, the priority of each wire network for wiring resource use is determined by utilizing the difference of the number of wire network 3D equivalent wiring schemes, and thus the number of through holes of a layer distribution scheme is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of computer-aided design of integrated circuits, in particular to a method for allocating parallel layers based on through-hole perception in ultra-large-scale integrated circuits. Background technique [0002] Layer assignment is an important stage in the VLSI physical design flow where each segment in each net is assigned to the appropriate metal layer. Layer assignment requires the use of vias to connect wires on different routing layers. The number of through holes used is an important factor affecting the manufacturing cost. Reducing the number of through holes is beneficial to save manufacturing cost. In addition, with the increasing scale of integrated circuits, the number of nets to be processed has increased significantly, and the increase in the running time of layer allocation algorithms has become an important factor limiting the efficient design of routing solutions. With the development of m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3947G06F30/392
CPCG06F30/3947G06F30/392
Inventor 刘耿耿李泽鹏郭文忠陈国龙
Owner FUZHOU UNIV
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