286 results about "Hyperscale" patented technology

An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the Linfin or the L1 metric instead of the Euclidean geometry.

Systems and / or methods for storing and / or retrieving assets in connection with an extremely large scale computer storage system are provided. An asset catalog may comprise a plurality of asset catalog entries stored according to at least one schema and corresponding to a plurality of assets. A storage architecture may be capable of storing the plurality of assets, with the storage architecture comprising a storage locator and a federator. An item identification scheme may be capable of providing identifiers to reference, locate, and / or access said assets and / or said asset catalog entries stored in the asset catalog in the storage architecture. The computer storage system may be scalable essentially without limitation while maintaining asset storage and retrieval flexibility and substantially obsolescence-proof survivability of assets.

The invention provides a distributed type storage system having a p2p function and a method thereof. The method is characterized in that: a client side sends a read-write request to a central server; the central server finds out the access address of the corresponding resource from a mapping table, and sends the access address to the client side; and according to the address of the storage node returned by the central server, the client side sends the read-write request to a particular storage node, the storage node sends a health condition report to the central server, and the central serverperforms the p2p scheduling of the resources on the storage nodes according to resource information for reading and writing and health condition information of all storage nodes. The system and the method have the advantages that: an ultra-large-scaled distributed type storage system can be formed by the integration of low-grade machines, the equipment can be easily maintained, and the infinite horizontal extension capability is ensured.

An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L INFINITY geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L INFINITY metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L INFINITY metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool. The critical area for the rectilinear approximation is computed using the preferred incremental method.

The invention provides a site selection and transportation optimization method for super-large scale logistics distribution. The method comprises the steps of clustering, side selection planning and route planning, specially, the method comprises the steps that computing is carried out with a method combined by a from-bottom-to-top clustering method and a designating-based clustering algorithm; a given distribution center number is p, the best site selection scheme is computed with minimum total cost as a target; site selection schemes with different distribution center numbers are compared, administration cost is integrated, an ideal site selection scheme is selected; according to the requirements of distraction point numbers in each cluster and geographic information, the time requirement of distribution connecting of each distribution point and the traffic time requirement between points are computed; an ant colony algorithm is used, and the best distribution route is obtained by computing. According to the site selection and transportation optimization method for super-large scale logistics distribution, the problem that computing amount is large caused by the fact that distribution points are increased greatly is effectively solved, compared with existing site selection-route planning, computing expenditure is greatly lowered, and efficiency is obviously improved.

The present invention relates to a chip of a three-dimensional multiprocessor system and belongs to the technical field of an integrate circuit design and manufacture. The present invention comprises a plurality of processor cores, a plurality of three-dimensional network routers on the chip and a wafer chip of a semiconductor integrate circuit that integrates a plurality of processor cores with a plurality of three-dimensional network routers on the chip. The present invention relates to a manufacturing method for utilizing wafer piles to assemble a three-dimensional integrate circuit and a transmitting method of parallel network data. The present invention has the advantages that: first, the part, whole or three-dimensional data transmissions are respectively accomplished by different channels, and the transmission congestion of the network data on the chip is relieved. Second, the three-dimensional chip structure reduces the chip area of a complicated SLSI (super-large-scale integration) and improves the product yield in the course of production. Third, the length of an interconnection line is shortened, the delay time of signals is reduced, and the system performance is enhanced.

A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Systems and / or methods for storing and / or retrieving assets in connection with an extremely large scale computer storage system are provided. An asset catalog may comprise a plurality of asset catalog entries stored according to at least one schema and corresponding to a plurality of assets. A storage architecture may be capable of storing the plurality of assets, with the storage architecture comprising a storage locator and a federator. An item identification scheme may be capable of providing identifiers to reference, locate, and / or access said assets and / or said asset catalog entries stored in the asset catalog in the storage architecture. The computer storage system may be scalable essentially without limitation while maintaining asset storage and retrieval flexibility and substantially obsolescence-proof survivability of assets.

The invention discloses a distributed parallel computing method and system for physical implementation of a large scale integrated circuit. According to the method, physical design problems of different stages are divided into sub-problems on a host, different division methods are applied to the different stages, then the sub-problems are sent to distributed servers by the host in a network communication mode to be computed, and computing results are sent back to the host. The host and a computing cluster are respectively provided with a servo management program, the program is an impotent component of a distributed computing frame and is in charge of management of distributed computing resources, and management of the distributed computing resources comprises resource allocation, resource recovery and the like. According to the distributed parallel computing method and system for physical implementation of the large scale integrated circuit, the physical design problems of a super-large scale integrated circuit can be solved rapidly and effectively, physical design efficiency of the integrated circuit can be improved greatly, and rapider and more-effective physical design of the large scale integrated circuit can be achieved compared with multithreading computing on a single computer.

The invention relates to the field of application of service provider social circle word-of-mouth marketing and family package recommendation marketing, particularly relates to a social network construction and family relationship identification method in word-of-mouth marketing, and discloses a user social network and family relationship construction method through user voice and short and multimedia message contact information. The method comprises the steps of calculation of the contact index, construction of a contact circle model, construction of a social network model and construction of a family relationship identification model. According to the technical scheme, the problems of efficient and robust construction of the social network and family relationship identification based on the contact information under the condition of large data volume of telephone bills of service providers can be solved.

The invention discloses a distributed network management system, which comprises at least two network management servers. The network management servers are mutually connected through communication links, and network management processing modules are respectively deployed in the network management servers. The system also comprises a scheduling module which is used for scheduling and deploying the service processes of the network management processing modules in all network management servers; the services provided by the same kind of the processing modules which process the bottleneck can be led to be separated in different processes by arranging the services provided by different network management processing modules into the different processes, thereby avoiding or reducing the bottleneck processing. Another distributed network management system comprises at least two network management servers as well as a service access coordinator, so as to enable each network manager service to be switched among each network management servers. The invention also provides a corresponding implementation method. The invention can carry out effective management to a super large scale network, so as to enable the dilation of the network management system to be smoother, thereby saving the hardware cost.

A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

The invention provides a distributed file storage system, which comprises a data storage server cluster subsystem and a file management server cluster subsystem, wherein the file management server cluster subsystem comprises at least two storage volumes; each storage volume at least comprises two storage node servers, the storage node servers in each volume are backups and mirror images of each other, and a difference of storage capacities of the storage node servers in each volume is smaller than a first set value; and the file management server cluster subsystem is used for customer file uploading, storage management and storage server cluster synchronization. The invention provides a large number of super-large scale extensible and loosely-coupled distributed file systems, the performance is greatly improved, the dynamic expansion is greatly improved, the system supports file second pass, streaming media real-time playing, oversized data file storage and multi-user file sharing andprotection, and the basic services are provided for a data storage technology of the present era of big data.

A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes.

The invention discloses a cloud drawing-based large-sized three-dimensional scene multi-person collaborative creation method, which relates to the field of three-dimensional visual scene creation and edition. The method comprises the following two major modules, i.e., a server and a client, wherein the server is an assembly consisting of a plurality of computers; the host in the assembly is divided into a scheduling host and a drawing host; the scheduling host is responsible for solving the problems of synchronization and mutual exclusion produced by editing the same three-dimensional scene by a plurality of users and distributing a drawing task to the drawing host; the drawing host is used for drawing a scene into an image according to visual angles of the users and transmitting to the corresponding client host; and the client host is used for providing an operation interface for three-dimensional scene creation. According to the method, combination of creation results of all the users is creatively and automatically finished at the server, and help can be provided for the users to observe the creation results of all the users in real time during creation; and the method has positive significance to multi-person collaborative creation of a super-large-sized scene.

Some embodiments of the invention provide a method for detecting and remediating anomalies in an SD-WAN that includes a controller, at least one enterprise datacenter, and multiple branch sites each having at least one edge node that includes a set of packet processing stages. At a particular node in the SD-WAN, the method receives, from the controller, trace monitoring rules specified for a particular packet flow. The method determines that a first packet received at the particular node belongs to the particular packet flow and matches at least one of the trace monitoring rules. Based on the determination, the method specifies the first packet as a packet that should be trace monitored by each packet processing stage of the particular node. As the first packet is processed by the set of packet processing stages, the method generates trace monitoring results to be provided to the controller for analysis.

The invention aims at disclosing a memory system for an ultra-large virtual machine cluster, and the memory system comprises a virtual machine cluster cache system, a virtual machine cluster mirror image memory system, a virtual machine cluster input / output (I / O) monitoring processing system and a distributive-type memory system. Compared with the prior art, the memory system has wide cloud computing virtual machine memory range, the access performance and the system stability of the virtual machine memory can be enhanced, rapidness in arrangement can be realized by a cloud computing vendor, the service can be provided according to the requirement, by reasonably combining a share memory way and an exclusive memory way, a memory architecture and the memory way change the passive memory to the active memory, the service quality is improved, the resource and the energy can be saved, and the purpose of the memory system can be realized.

A medium- and long-distance super-capacity universal wireless sensor network comprises base station nodes, sensor nodes and a network control center. The base station nodes are network coordinator nodes used for establishing and managing a local network, communicating with wireless sensor nodes in a range covered, forwarding query command of the network control center and sending query information back to the network control center. The wireless sensor nodes are used for sending related information of carriers to base stations. The network control center is used for full-network channel resource configuration and full-network terminal user management and for communication with an external network. The invention further provides a communication method of the medium- and long-distance super-capacity universal wireless sensor network. Provided are the medium- and long-distance super-capacity universal wireless sensor network allowing large-area coverage and having super-scale capacity and compatibility with different applications and the communication method thereof; the network employs a low-power medium- and long-distance wireless communication technique.

Some embodiments of the invention provide a method for detecting and remediating anomalies in an SD-WAN that includes a controller, at least one enterprise datacenter, and multiple branch sites each having at least one edge node that includes a set of packet processing stages. At a particular node in the SD-WAN, the method receives, from the controller, trace monitoring rules specified for a particular packet flow. The method determines that a first packet received at the particular node belongs to the particular packet flow and matches at least one of the trace monitoring rules. Based on the determination, the method specifies the first packet as a packet that should be trace monitored by each packet processing stage of the particular node. As the first packet is processed by the set of packet processing stages, the method generates trace monitoring results to be provided to the controller for analysis.

The invention discloses a layout legalization method and system for distributed computing of a large-scale integrated circuit. Firstly, all master pairs are enumerated according to a master of unit modules, each master pair serves as a Master pair subtask, and minimum spacing without regions violating design rules in different rotation directions is calculated and stored into a Hash locating table based on bit storage; secondly, the whole layout region is divided into a plurality of layout lines, each layout line serves as a layout subtask, whether the spacing between adjacent unit modules in each layout subtask is equal to the value stored in the Hash locating table is calculated, and if not, the unit modules are rotated or moved, so that all the regions violating the design rules created due to an unreasonable layout are eliminated. By means of the layout legalization method and system, layout legalization of a super-large-scale integrated circuit can be achieved quickly and effectively, and meanwhile better wiring through wiring units at process nodes with the interconnection wire width of 65 nm or below can be facilitated.

The invention discloses a multi-process self-adaptive allocation super-large-scale integrated circuit field-circuit coupling method, which perfectly realizes a rapid and accurate calculation target offield-circuit coupling of multi-layer super-large-scale integrated circuit direct-current field analysis by simplifying a three-dimensional problem into a two-dimensional problem and adopting a super-node technology. Field circuit coupling can be accurately and completely carried out on the multi-layer integrated circuit direct-current electric field, and the calculation speed of the multi-layerintegrated circuit and chip packaging direct-current electric field is increased. Meanwhile, coarse particle parallelism is achieved in the operation process, communication between processes and waiting time generated by synchronization are reduced to a great extent, meanwhile, due to the fact that a calculation task random dynamic allocation method is adopted, it is guaranteed that calculation models with unequal complexity are randomly and evenly distributed on all calculation nodes, and calculation efficiency is improved. And a hard disk read-write bottleneck caused by virtual memory accessdue to an overhigh peak memory is avoided.

The invention provides a cloud computing system-based data acquisition system and a data acquisition method thereof. The system comprises a host node subsystem and a slave node subsystem which are arranged on a host node and a slave node of a cloud computing system respectively, wherein the host node subsystem comprises a connecting intelligent library module, a processing intelligent library module, a storage intelligent library module, an intelligent analyzing and decision-making module and a cloud computing auxiliary management host node module; and the slave node subsystem comprises a foreground connecting module, a data processing module, a background storing module and a cloud computing auxiliary management secondary module. The system is characterized by adopting an intelligently analyzed decision to provide efficient information to a task decision of a user, processing mass data by taking advantage of super-large scale of the cloud computing system at the same time and solvingthe problem of influence of continuous increase in the data on the performances of the system.

A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The exemplary method also includes generating statistics for the set of components. The statistics are related to clock gating testing to identify whether one or more components of the set of components can be clock gated.

The invention provides a rapid mapping method and system for super-large-scale spatial data. The method comprises the following steps: obtaining a vector tile map on line, wherein the vector tile mapcomprises vector tile data and tile style data; determining tile hierarchies corresponding to the drawing requirements and row and column ranges in the tile hierarchies; Retrieving vector tile data and tile style data corresponding to the tile levels and the row and column ranges from the vector tile map; splicing the vector tile data to generate a grid map; and trimming the grid map to generate aspatial data drawing result. According to the method, drawing is carried out based on the online vector tile map, real-time dynamic rendering of the drawing style is carried out according to the drawing requirement, the calculated amount is only related to the retrieved tile level and range, the calculation process is simple, the problem that the data processing amount is large due to the fact that traditional drawing is firstly shrunk and then drawn is solved, and the spatial data drawing efficiency is improved.

Some embodiments of the invention provide a method for detecting and remediating anomalies in an SD-WAN that includes a controller, an enterprise datacenter, and multiple branch sites each having at least one edge node that includes a set of packet processing stages. At the controller, the method receives from a particular node of a particular branch site a flow notification indicating detection of an anomaly on the particular node. Based on the anomaly, the method dynamically generates trace monitoring rules that specify one or more flows to be traced and provides the trace monitoring rules to the particular node and at least one other node of another branch site. From the particular node and the at least one other node, the method receives trace monitoring results collected in response to the provided trace monitoring rules, and analyzes the results to identify any anomalies and dynamic actions to correct the anomalies.

The invention provides a system based on a whole cabinet server ultra-large-scale deployment, and belongs to the technical field of a whole cabinet server ultra-large-scale deployment. The system uses a modular design manner, and is divided into six parts including a cabinet module, a network module, a power supply module, a server node module, a centralized fan heat dissipating module, and a centralized management module. The invention meets the demand of large scale Internet application and data center building, and standardization is achieved in a larger range by the modular design to ensure that customers get lower procurement cost, higher purchasing efficiency and faster deployment efficiency.

The invention discloses methods for automatically detecting the topology of optical transmission monitoring networks and an implementation device. The methods comprise a central site topological method and an ordinary node topological method, wherein a central node is used for initiating a topological query from a central node and downwards routing from a central main site according to a policy of sub-path priority and breaking path return; if the node has multiple sub topological structures, different priority levels of the sub topological structures can be defined, and the priority levels are sequentially traversed from high levels to low levels. The topological routing algorithm can guarantee that all nodes in an optical network can be traversed under the condition of any open path or closed loop and the traversing sequence is consistent with a pseudo coding sequence. The invention also discloses the device for implementing the method for automatically detecting the topology of the optical transmission monitoring networks. The invention is realized based on a synchronous clock transmission system and a hardware structure, has various characteristics of high topology speed (ns level), high reliability, support of chain type, ring type, ring cutting, star-shaped and mixed type optical networks, low implementation cost, and the like and is suitable for the intelligent topology processing of large and medium scaled and even very-large-scaled monitoring optical transmission networks in the field of security.

The invention provides an integrated circuit self-adaptive finite element mesh subdivision method based on posterior error estimation. The method comprises the following steps: step 1, solving to obtain a finite element numerical solution of a mesh unit; in the super-convergence unit sheet of each grid node, approximately recovering a gradient Gspr with higher-order precision as an accurate valueof the gradient of the solution based on the gradient Gfem of the solution; 2, calculating a relative error and an overall error of each grid cell unit, judging whether an overall error index reachesthe standard or not, If so, ending; 3, iteratively calculating the one-time subdivision frequency of each grid unit; 4, smoothing the subdivision times of the grid units, so that the difference between the subdivision times of the adjacent grid units is not higher than 1; step 5, directly subdividing each grid unit based on the subdivision times of the grid units; step 6, smoothing the subdividedgrid units; 7, turning to the step 1. According to the method, the solution meeting the precision requirement can be obtained through one-time grid cell subdivision and solving, and the solving time of the electromagnetic field problem of the super-large-scale integrated circuit is shortened.

The invention discloses a random dynamic allocation method for frequency domain simulation calculation tasks of a super-large-scale integrated circuit. An operation program is divided into a pluralityof parallel coarse particles which are not overlapped with one another and execute independent operation; layout projection, triangulation operation, grid alignment, layer information superposition,parallel flat plate field domain recognition and parallel flat plate field domain adaptive grid subdivision processing are carried out; all parallel flat plate field domains can be quickly identifiedat one time. The problem that gaps cannot be formed between the parallel plate field domains which should be mutually coupled due to errors of numerical calculation is avoided. Meanwhile, different parallel coarse particles are used for calculating at different levels, so that the communication between processes and the waiting time caused by synchronization are reduced, and the hard disk read-write bottleneck caused by virtual memory access due to an overhigh peak memory is also avoided.