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A pcie error note testing method, device and storage medium

A test method and technology of a test device, which are applied in the field of PCIe error injection testing, can solve problems such as unrealizable, expensive, and uncorrectable error testing, and achieve the effect of improving reliability

Active Publication Date: 2022-04-29
WARECONN TECH SERVICE (TIANJIN) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, ITP tools are expensive and can be tested for correctable errors during the test process, but cannot be tested for uncorrectable errors.

Method used

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  • A pcie error note testing method, device and storage medium
  • A pcie error note testing method, device and storage medium
  • A pcie error note testing method, device and storage medium

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Embodiment Construction

[0047] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0048] In the description of the embodiments of the present invention, it should be noted that unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection ; It can be a mechanical connection, or an e...

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PUM

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Abstract

A PCIe error injection testing method, device and storage medium. Described PCIe wrong note testing method comprises and builds wrong test platform according to the target information of receiving; Note wrong test platform comprises at least one test system and control system; When detecting setting instruction, the safe start of setting test system is disabled state ; Obtain and display PLX bus information; bus information includes multiple groups of test objects; select a group of test objects according to the bus information when a position selection instruction is detected; when detecting a wrong note selection instruction, control the test object to simulate at least one note Error test items; error injection test items include correctable error injection test items and uncorrectable error injection test items; obtain and analyze PCIe error injection results.

Description

technical field [0001] The invention relates to a PCIe error injection testing method, device and storage medium. Background technique [0002] The high-speed serial computer expansion bus standard (peripheral compoment interconnect express, PCIe) device is used as the main IO (input output) bus connecting the CPU (central processing unit) and various devices on the server because of its high speed and high bandwidth. A PCIe device can be plugged into any PCIe slot of the server, so a server can be equipped with multiple PCIe devices. A server must simulate the user's use process during the R&D stage and the production stage, and then test the new RAS performance of the server. Among them, RAS stands for Reliability (credibility), Availability (available) and Service-ability (service capability). Compared with a server test platform, the RAS feature of the platform is a feature that can be set, which can increase the credibility of the platform. , availability and servicea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40G06F11/22
CPCG06F13/4018G06F11/2221G06F11/221G06F11/263G06F13/4282G06F2213/0026
Inventor 杨承达陈燕炫
Owner WARECONN TECH SERVICE (TIANJIN) CO LTD