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CPU instruction implementation method supporting multi-data access

A multi-data and instruction technology, applied in the fields of computer software, instruction compiler design, and CPU instruction set design, can solve problems such as inefficiency and complex implementation methods

Inactive Publication Date: 2020-10-27
北京芯启科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The implementation of the traditional general-purpose instruction set is complex and inefficient

Method used

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  • CPU instruction implementation method supporting multi-data access
  • CPU instruction implementation method supporting multi-data access
  • CPU instruction implementation method supporting multi-data access

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Embodiment Construction

[0034] The present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0035] figure 1 It is the basic instruction bit field definition based on the basis of RISC and the commonly used instruction set. In this definition, the expression form of 32 instruction bits is taken as an example.

[0036] On this basis, the requirements for supporting multiple data access are very diverse, and the required multiple data operation instructions have the following characteristics:

[0037] According to the data type of the access operation, it is divided into two categories: the minimum support for the byte data required for calculation, such as half float is 2 bytes in length; the most commonly supported single-shot data transmission length that the bus can support, such as 4 bytes commonly used in embedded length.

[0038] According to the length setting method, it is divided into two categories: directly specify the registe...

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Abstract

A CPU instruction implementation mode supporting multi-data access is provided. The design of the invention can meet the requirement for providing efficient data reading or storing back for a hardwareacceleration calculation execution unit, and the circuit design is greatly simplified through specific design of an instruction bit function. The design of the invention comprises the following stepsof: realizing a multi-data access instruction, and carrying out specific design aiming at operands and operation mode characteristics in the field of computation; according to the execution unit device supporting the instruction, the structure of a connection circuit is simplified, and the area and power consumption are saved.

Description

technical field [0001] The invention belongs to the fields of computer software, CPU instruction set design, instruction compiler design, and digital integrated circuit design, and in particular relates to a CPU instruction implementation method supporting multi-data access. Background technique [0002] With the rise of domain-specific processors, the expansion and optimization of the instruction sets for such processors are different for different domains. The implementation of the traditional general-purpose instruction set is complicated and inefficient. By analyzing the control and data requirements in the deep convolutional neural network hardware acceleration computing tasks, and the working characteristics of the central processing unit that needs to perform special processing on data, the present invention implements the access instructions in the CPU instruction set within the RISC framework. expand. Contents of the invention [0003] The invention provides a C...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30181
Inventor 伍世聪林森李珏
Owner 北京芯启科技有限公司
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