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Memory-side transaction context memory interface systems and methods

A memory system and memory technology, applied in the field of computing systems, can solve problems such as operational efficiency limitations

Pending Publication Date: 2020-11-17
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, at least in some cases, the operational efficiency of a computing system may be limited by its architecture, which governs, for example, the sequence of operations performed in the computing system

Method used

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  • Memory-side transaction context memory interface systems and methods
  • Memory-side transaction context memory interface systems and methods
  • Memory-side transaction context memory interface systems and methods

Examples

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Embodiment Construction

[0022] The present disclosure provides techniques that facilitate increasing computing system operational efficiency, for example, by mitigating architectural features that might otherwise limit operational efficiency. In general, computing systems may include various subsystems, such as processing subsystems and / or memory subsystems. In particular, a processing subsystem may include, for example, processing circuitry implemented in one or more processors and / or one or more processor cores. A memory subsystem may include, for example, one or more memories implemented on a memory module such as a dual inline memory module (DIMM) and / or organized to implement one or more memory arrays such as an array of memory cells device (eg, chip or integrated circuit).

[0023] Generally, during operation of a computing system, processing circuitry implemented in its processing subsystems may perform various operations by executing corresponding instructions currently stored in one or more...

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Abstract

Techniques for implementing and / or operating an apparatus, which includes a memory system coupled to a processing system via a memory bus. The memory system includes hierarchical memory levels and a memory controller. The memory controller receives a memory access request at least in part by receiving an address parameter indicative of a memory address associated with a data block from the memorybus during a first clock cycle and receiving a context parameter indicative of context information associated with current targeting of the data block from the memory bus during a second clock cycle,instructs the memory system to output the data block to the memory bus based on the memory address indicated in the address parameter, and predictively controls data storage in the hierarchical memorylevels based at least in part on the context information indicated in the context parameter of the memory access request.

Description

technical field [0001] The present disclosure relates generally to computing systems, and more particularly, to memory interfaces implemented in computing systems. Background technique [0002] In general, computing systems include a processing subsystem and a memory subsystem that can store data that can be accessed by the processing circuitry of the processing subsystem. For example, to perform operations, processing circuitry may execute corresponding instructions retrieved from memory devices implemented in a memory subsystem. In some cases, data input for the operations may also be retrieved from a memory device. Additionally or alternatively, data output from (eg, resulting from) the described operations may be stored in a memory device, eg, to enable subsequent retrieval. However, at least in some cases, the operational efficiency of a computing system may be limited by its architecture, eg, the architecture governing the sequence of operations performed in the comp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0877G06F12/0893
CPCG06F12/0877G06F12/0893G06F13/1615G06F2212/6026G06F12/0862G06F2212/6022G06F2212/1016G06F2212/6024G06F2212/602
Inventor D·A·罗伯茨
Owner MICRON TECH INC
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