A method and system for checking timing violations of multi-bit signals across clock domains

Abstract

The invention discloses a method and system for checking timing violations of multi-bit signals across clock domains. The invention includes: obtaining all timing signoff corners; Perform the following processing: calculate the average clock insertion delay of each clock domain named characteristic sequence unit; remove the asynchronous constraints between different clock groups, do not check the internal timing of the clock domain; establish cross-clock domain clock groups, and control and Different timing check constraints are set for data signals; setup and hold time violation checks for all cross-clock domain clock packets are performed for control and data signals. Outputs the timing check results of signals crossing clock domains. The invention is used in the process of checking the timing of cross-clock domain signals, which can not only ensure the correct transmission function of cross-clock domain signals, but also not expose a large number of false cross-clock domain signal timing violations due to the problem of over-constraint, and avoid repairing timing Large number of buffers inserted by violation.

Description

technical field [0001] The invention belongs to the cross-clock domain signal timing analysis and inspection technology in the field of digital integrated circuit design, and specifically relates to a method and system for checking cross-clock domain multi-bit signal timing violations. Background technique [0002] As we all know, there are many clock domains in the SOC (system on chip), and the signal transmission circuit between two clock domains with different frequencies or uncertain phase relationship is called a cross-clock domain circuit. Such as main clock and generated clock, asynchronous clock, I / O interface. Due to the uncertainty of the arrival time of the signal transmitted across the clock domain, it cannot be guaranteed that the sampling signal remains stable before the rising or falling edge of the destination clock arrives, thus causing a violation of the setup time and hold time of the sampling register. This instability, known as metastability, often caus...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention: Aiming at the above-mentioned problems in the prior art, a method and system for checking timing violations of cross-clock domain multi-bit signals are provided, which are used to ensure that The cross-clock domain signal transmission function is correct, and it does not expose a large number of false cross-clock domain signal timing violations due to over-constraint problems, avoiding a large number of buffers inserted by repairing timing violations

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