Method for remotely programming and loading FPGA and DSP

Abstract

The invention discloses a method for remotely programming and loading an FPGA and a DSP. The method comprises the following steps that: a first FLASH program memory in a signal processor comprises a first FPGA hardware partition, a second FPGA hardware partition and a third FPGA hardware partition, wherein the first FPGA hardware partition is used for storing FPGA jump and programming programs; the second FPGA hardware partition is used for storing effective marks of FPGA formal program storage blocks; and the third FPGA hardware partition is used for storing a plurality of FPGA formal programs. A second FLASH program memory in the signal processor comprises a first DSP hardware partition for storing DSP jump and programming programs, a second DSP hardware partition used for storing DSP formal program storage block effective marks and DSP formal parameter storage block effective marks, a third DSP hardware partition used for storing a plurality of DSP formal programs, and a fourth DSPhardware partition used for storing a plurality of DSP formal parameters. Remote and reliable programming, loading and switching of formal programs / parameters can be carried out in one storage block,and other storage blocks are not influenced.

Description

Technical field[0001]The present invention relates to the field of information technology, in particular to a method for remote programming, loading and switching between FPGA and DSP programs.Background technique[0002]Modern radar signal processors have formed a mainstream architecture with FPGA (Field-Programmable Gate Array) + DSP (Digital Signal Processing) as the core. FPGA and DSP program debugging and programming are mainly based on JTAG (Joint Test Action Group, joint test working group) bus. In the long-distance transmission, the JTAG bus has poor anti-interference ability and high bit error rate, which will increase the burden on the structure of the radar machine and the design of software and hardware after being led out, so it is not suitable for the external programming bus of the radar machine. With the advancement of radar technology, signal processor algorithms are becoming more and more complex, and it is difficult to build a verification environment close to real ...

AI Technical Summary

Problems solved by technology

[0003] At present, there is only one official program in the FLASH program memory of FPGA and DSP, which is stored in a fixed address space. Before programming a new program, the original program needs to be erased. There is no risk of formal procedures available, and it is not suitable for reliable and rapid updates and upgrades in the use of important equipment, nor is it suitable for the rapid verification of multiple schemes of the radar machine and the rapid switching of program algorithms according to the deployment environment

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