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Chip power network layout method and device

A power supply network and chip technology, applied in the direction of electrical digital data processing, CAD circuit design, special data processing applications, etc., can solve the problems of increased timing deviation and large voltage drop, and reduce timing deviation and power supply voltage. drop, good balance effect

Pending Publication Date: 2020-12-22
深圳天狼芯半导体有限公司
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Problems solved by technology

[0004] Therefore, the traditional chip power network layout method has an excessively large voltage drop at an ultra-low operating voltage, resulting in a substantial increase in timing deviation.

Method used

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  • Chip power network layout method and device
  • Chip power network layout method and device

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Embodiment Construction

[0040] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0041] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude one or more other Presence or addition of features, wholes, steps, operations, elements, components and / or collections thereof.

[0042] It should...

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Abstract

The invention is suitable for the field of integrated circuit design and layout, and provides a chip power network layout method and device, and the method comprises the steps of firstly dividing a chip into a plurality of power regions according to the size of the chip; arranging at least one power supply distribution circuit in each power supply area, wherein each power supply distribution circuit provides power supply voltage for a plurality of logic circuits in a power supply area where the power supply distribution circuit is located; connecting the voltage input ends of the power distribution circuits to form a voltage input network; connecting the voltage output ends of the source distribution circuits to form a voltage output network; and finally connecting the voltage output network and the control circuit to enable the control circuit to adjust the power supply voltage according to feedback of the voltage output network. The logic circuits in all the power supply areas are supplied with power supply voltage by the voltage output network, and the power supply of each logic circuit is better balanced, so that the power supply voltage drop of the logic circuits is reduced under the ultralow working voltage, and the time sequence deviation is reduced.

Description

technical field [0001] The present application belongs to the technical field of integrated circuit design and layout, and in particular relates to a chip power network layout method and device. Background technique [0002] Because traditional chips work under the normal power supply voltage, the power supply voltage is usually provided by an external low drop out regulator (LDO) or a DC step-down converter, and then the metal layer inside the chip will The power supply voltage input from the outside is introduced into the chip. [0003] During this whole process, due to the parasitic resistance and the resistance of the metal layer itself (the resistance is composed of the power line and the power network), a voltage drop will inevitably occur, causing the power supply voltage to be different from the logic actually connected to the device. There is a voltage difference between the voltages of the circuit, this voltage difference is below the normal power supply voltage, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06F115/02
CPCG06F30/392G06F2115/02
Inventor 曾健忠
Owner 深圳天狼芯半导体有限公司
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