PCIE signal PIN adjacent layer hollowing design method, system and device and storage medium

Abstract

The invention discloses a PCIE signal PIN adjacent layer hollowing design method, system and device and a computer readable storage medium. The PCIE signal PIN adjacent layer hollowing design method comprises the steps that: PIN design information of a high-speed PCIE signal line in design parameters of a PCB is acquired; the PIN design information is utilized to obtain hollowing information of hollowed-out areas in hollowed-out layers corresponding to each pair of differential line PINs, wherein the hollowing information comprises the number, the size and the position information of the hollowed-out areas. According to the PCIE signal PIN adjacent layer hollowing design method, system and device and the storage medium, the PIN design information of the high-speed PCIE signal line can be extracted from the PCB according to the design parameters of the PCB, the hollowed-out layers and the hollowed-out areas are automatically planned according to the PIN design information; automatic hollowing design is achieved; errors caused by human factors are avoided; the design speed is increased; and the working efficiency is improved.

Description

technical field [0001] The invention relates to the field of electronic information, in particular to a method, system, device and computer-readable storage medium for hollowing out the adjacent layer of a PCIE signal PIN. Background technique [0002] Existing high-speed signals of SLOT, such as PCIE4.0, in order to control the impedance of the PCIE signal PIN of SLOT, it is necessary to hollow out the adjacent ground, because the width of the signal PIN is large, resulting in a small impedance of the differential line, if the adjacent ground Hollow out, so that the signal PIN refers to the next layer of the adjacent layer, which is generally the third or fourth layer, or the third and fourth layers from the bottom, so that the thickness of the medium from the reference layer increases, which increases the impedance, which can Balance the impedance of PCIE4.0 high-speed signals. [0003] As there are more and more types of high-speed signals, there are more and more high-s...

AI Technical Summary

Problems solved by technology

[0003] As there are more and more types of high-speed signals, there are more and more high-speed differential signal lines, and the number of SLOTs on each board is also increasing, and there are more and more high-speed signals. The design efficiency is low according to the existing technology , even if you make one well and enter the coordinate command to copy it, it will take a long time and it is error-prone

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