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Fusion multiply-add operator with correctly rounded mixed precision floating-point number

An arithmetic unit and floating-point number technology, which is applied in the direction of instruments, calculations, electrical digital data processing, etc., can solve problems that do not mention the specific size of the adder

Pending Publication Date: 2020-12-25
KALRAY
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Problems solved by technology

[0012] The above patent application does not mention any particular size of the adder

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  • Fusion multiply-add operator with correctly rounded mixed precision floating-point number
  • Fusion multiply-add operator with correctly rounded mixed precision floating-point number
  • Fusion multiply-add operator with correctly rounded mixed precision floating-point number

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Embodiment Construction

[0033] In order to improve computational accuracy during the multiple stages of accumulation of partial products, it is desirable to implement a mixed-precision FMA, ie, an addition operand with higher precision than the multiplicand. In fact, during repeated accumulation, the addition operands tend to increase continuously, while the partial products remain bounded.

[0034] The above IEEE article by Nicolas Bruni proposes a solution that provides accurate computation of multiplicands suitable for binary 16 format, the product of which can be represented in an 80-bit fixed-point format, a format that is not difficult for processors to It is still acceptable for hardware processing within the core's processing unit.

[0035] However, the product of two binary 16s produces a non-standard floating point number with a sign bit, 6 exponent (exponent) bits, and 21+1 mantissa (mantissa) bits, encoded on 28 bits. This format is only used internally. Then, expect the addition operan...

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Abstract

A fusion multiply-add hardware operator comprising a multiplier receiving two multiplicands as floating-point numbers encoded in a first precision format; an alignment circuit associated with the multiplier configured to convert the result of the multiplication into a first fixed-point number ; and an adder configured to add the first fixed-point number and an addition operand. The addition operand is a floating-point number encoded in a second precision format , and the operator comprises an alignment circuit associated with the addition operand, configured to convert the addition operand into a second fixed-point number of reduced dynamic range relative to the dynamic range of the addition operand, having a number of bits equal to the number of bits of the first fixed-point number, extended on both sides by at least the size of the mantissa of the addition operand; the adder configured to add the first and second fixed-point numbers without loss.

Description

technical field [0001] The present invention relates to the hardware arithmetic unit that is used for processing floating-point number in processor core, relates to be used for being based on the fused multiply-add operation commonly called FMA (Fused Multiply-Add operator, fused multiply-add operator) more particularly operator to calculate the dot product. Background technique [0002] Artificial intelligence techniques, especially deep learning, are particularly demanding when it comes to the multiplication of large matrices, which can have hundreds of rows and columns. As a result, hardware accelerators specialized in mixed-precision matrix multiplication are emerging. [0003] Multiplication of large matrices is usually implemented in blocks, that is, by decomposing the matrix into submatrices of a size appropriate to the computational resources. Accelerators are therefore designed to efficiently compute the product of these sub-matrices. Such an accelerator includes...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/485G06F7/487
CPCG06F7/485G06F7/4876G06F7/5443G06F7/483G06F7/49936G06F7/49947
Inventor N.布鲁尼
Owner KALRAY
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