A hardware parsing method for binary protocol data stream
An analysis method and data flow technology, which is applied in the analysis field of Binary protocol data flow, can solve problems such as resource occupation and large delay, and achieve the effects of improving processing capacity, reducing processing delay, and improving decoding efficiency
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[0024] The hardware that can be selected in this embodiment is FPGA or special-purpose AISC, preferably FPGA in this embodiment, FPGA device belongs to a kind of semi-custom circuit in application-specific integrated circuit, is a programmable logic array. During implementation, the corresponding execution program is downloaded into the FPGA, and the FPGA is configured to have an input interface buffer, a decoding module and an output interface buffer, and the input interface buffer is used to store the original Binary protocol data stream received, the said The decoding module is used to perform field matching on the data stream according to the Binary protocol, and the output interface cache is used to cache the matched fields.
[0025] Such as figure 2 As shown, the input interface cache adopts the standard AXI-Stream interface FIFO memory, which has fast data speed and strong external portability, and can be directly connected to existing PCI-E devices or Ethernet devices...
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