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A hardware parsing method for binary protocol data stream

An analysis method and data flow technology, which is applied in the analysis field of Binary protocol data flow, can solve problems such as resource occupation and large delay, and achieve the effects of improving processing capacity, reducing processing delay, and improving decoding efficiency

Active Publication Date: 2022-03-29
山东产研集成电路产业研究院有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These transaction data are formatted through the Binary protocol (Binary protocol to format the business demand process, making it a functional process that can be described in computer language, and uniformly exchange the format on each business function interface. Refer to the engineering technical standard "Shenzhen Securities Exchange The Binary transaction data interface specification (Ver1.13)") is transmitted and further processed by the computer. Due to the huge amount of transaction data, it will cause serious resource occupation and large delays.

Method used

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  • A hardware parsing method for binary protocol data stream
  • A hardware parsing method for binary protocol data stream
  • A hardware parsing method for binary protocol data stream

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Embodiment

[0024] The hardware that can be selected in this embodiment is FPGA or special-purpose AISC, preferably FPGA in this embodiment, FPGA device belongs to a kind of semi-custom circuit in application-specific integrated circuit, is a programmable logic array. During implementation, the corresponding execution program is downloaded into the FPGA, and the FPGA is configured to have an input interface buffer, a decoding module and an output interface buffer, and the input interface buffer is used to store the original Binary protocol data stream received, the said The decoding module is used to perform field matching on the data stream according to the Binary protocol, and the output interface cache is used to cache the matched fields.

[0025] Such as figure 2 As shown, the input interface cache adopts the standard AXI-Stream interface FIFO memory, which has fast data speed and strong external portability, and can be directly connected to existing PCI-E devices or Ethernet devices...

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Abstract

The invention relates to a hardware parsing method for Binary protocol data streams. The process is as follows: download the decoding program to FPGA or solidify it into ASIC (need to be streamed), the Shenzhen Stock Exchange server sends transaction data streams, and passes through the network interface or PCI‑ The E interface is input to FPGA or ASIC, cached in the input interface cache, the length of each data packet is adjusted through the packet reorganization module, and then enters the decoding module, which performs data stripping and decoding according to the above steps, and the decoded data is sent To the output interface buffer, and output to the client CPU through the network interface or PCI‑E interface, the decoded data can be obtained. The invention greatly improves the decoding speed through special hardware decoding, can reduce the burden on the computer, and has great economic benefits.

Description

technical field [0001] The invention relates to an analysis method of Binary protocol data flow, in particular to a hardware analysis method. Background technique [0002] With the development of my country's economy, the securities industry has made great progress. Shenzhen Stock Exchange (hereinafter referred to as "Shenzhen Stock Exchange"), as one of the main trading places in my country, generates a large amount of transaction data every day. These transaction data are formatted through the Binary protocol (Binary protocol to format the business demand process, making it a functional process that can be described in computer language, and uniformly exchange the format on each business function interface. Refer to the engineering technical standard "Shenzhen Securities Exchange The Binary transaction data interface specification (Ver1.13)") is transmitted and further processed by the computer. Due to the huge amount of transaction data, it will cause serious resource occ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40H04L69/06H04L69/22
CPCG06F13/4068G06F13/4009H04L69/06H04L69/22
Inventor 滕达温士魁
Owner 山东产研集成电路产业研究院有限公司