Multi-power-domain layout method and storage medium

A layout method and multi-power supply technology, applied in the field of electronics, can solve the problem of not being able to ensure that all cells are in the design position

Active Publication Date: 2020-12-25
BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +3
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the embodiment of the present invention is to provide a multi-power domain layout method to at least solve the above-mentioned problem that the current multi-power domain design under non-UPF cannot ensure that all cells are in the design position

Method used

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  • Multi-power-domain layout method and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] Embodiment one: if Image 6 As shown, it shows possible errors and corrections that may occur in the signal interaction between the always on1 area inside the IP and the always on area inside the Digital. For this problem, if Figure 7 , the EDA tool runs the check.tcl script to check whether there is a cell placement error, counts the boundaries of the shutdown area, and counts the pins connected to the always on area from the always on1 area, uses the if statement to determine the direction of the pin, and inputs the pin using the all_fanin command to track all the inputs The pin on the chain and the output pin use the all_fanout command to track all the pins on the output chain, and then trace the pin to the corresponding cell (excluding the IP itself). Perform logical AND operation on the output cell boundary and the shutdown area boundary, use the if statement to judge, if the result is not equal to 0, print out the information of the wrong cell.

Embodiment 2

[0051] Embodiment two: if Figure 8 As shown, it shows that the possible error in the signal interaction between the shutdown1 area inside the IP and the shutdown area inside the Digital is: the EDA tool places the cell communicating between the two areas in the always on area, and the correct location should be in the shutdown area . For this error, such as Figure 9 , the EDA tool runs the check.tcl script to count the boundaries of the shutdown area, count the pins connected to the shutdown area in the shutdown1 area, use the if statement to determine the direction of the pin, use the all_fanin command to track all pins on the input chain for the input pin, and use all_fanout for the output pin The command traces all the pins on the output chain, and then traces the pin to the corresponding cell (not including the IP itself). The two types of cells calculate the boundary information and name information one by one, and compare the calculated cell boundary with the shutdown...

Embodiment 3

[0052] Embodiment three: as Figure 10 , showing that the possible error in the signal interaction between the always on1 area inside the IP and the shutdown area inside the Digital is: the EDA tool places the cell communicating between the two areas in the always on area, and the correct location should be in the shutdown area. For this problem, if Figure 11 , the EDA tool runs the check.tcl script, counts the boundaries of the shutdown area, counts the pins connected to the shutdown area in the always on1 area, uses the if statement to determine the direction of the pin, and uses the all_fanin command to track all pins on the input chain for the input pin, and uses the output pin The all_fanout command traces all the pins on the output chain, and then traces the pin to the corresponding cell (excluding the IP itself). The two types of cells count the boundary information and name information one by one, and compare the calculated cell boundary with the shutdown area boundar...

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Abstract

The invention provides a multi-power-domain layout method and a storage medium, and belongs to the technical field of electronics. The method comprises the following steps: S1) reading multi-power domain layout design data, and setting PG regions of different power regions according to the multi-power domain layout design data; S2) according to a physical design rule, sequentially executing each layout stage of the multi-power domain layout, and after each layout stage is completed, obtaining completion information of the layout stage and performing error unit screening on the completion information to obtain error unit statistical information of the layout stage; modifying the design information according to the statistical information of the error units; and S3) after the design information of all the layout stages is modified, performing static timing sequence analysis and physical verification on the modified design information, judging whether timing sequence and design rule errors exist or not, and executing error repair when errors are found until all the errors are repaired. The problem that it cannot be guaranteed that all cells are located at the design positions throughmulti-power-supply-domain design under the current non-UPF condition is solved.

Description

technical field [0001] The present invention relates to the field of electronic technology, in particular to a multi-power domain layout method and a computer-readable storage medium. Background technique [0002] Multi-power domain design has strong practical significance for reducing power consumption in integrated circuits. Currently, EDA (Electronic design automation, electronic design automation) tools are used to design multi-power domains based on the UPF (Unified PowerFormat, unified power consumption mode) process. , but some process libraries do not contain the isolation unit required for the UPF process, and the UPF power shutdown design method cannot be used. At this time, the isolation unit needs to be instantiated manually in the front-end design, and the logic connected to the isolation unit is checked in the physical design stage. The physical position of the unit enables the chip to normally and reasonably control the power supply shutdown under different wo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F30/392G06F30/3315
CPCG06F30/3315G06F30/392G06F30/398
Inventor 郑礼坤徐一李德建胡旭唐晓柯胡毅
Owner BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY
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